[Commit-gnuradio] r9100 - in usrp2/trunk/fpga/eth/rtl/verilog: . MAC_rx

[matt]

Author: matt
Date: 2008-07-31 20:29:50 -0600 (Thu, 31 Jul 2008)
New Revision: 9100

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
Log:
pass fifo information out


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-08-01 02:27:42 UTC 
(rev 9099)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-08-01 02:29:50 UTC 
(rev 9100)
@@ -16,7 +16,7 @@
      input         Fifo_data_err,
      input         Fifo_data_end,
      output [15:0] Fifo_space,
-     
+
      // CPU
      input         RX_APPEND_CRC,
      input [4:0]   Rx_Hwmark,
@@ -29,7 +29,12 @@
      output [1:0]  Rx_mac_BE,
      output        Rx_mac_sop,
      output        Rx_mac_eop,
-     output        Rx_mac_err
+     output        Rx_mac_err,
+
+     // FIFO Levels
+     output [15:0] fifo_occupied,
+     output fifo_full_dbg,
+     output fifo_empty
      );
 
    reg [1:0]      FF_state;       
@@ -114,7 +119,7 @@
    
    wire           sop_o, eop_o, empty;
    wire [1:0]     be_o;
-   wire [RX_FF_DEPTH-1:0] occupied;
+   wire [RX_FF_DEPTH-1:0] occupied, occupied_sysclk;
    wire [31:0]            dataout;
 
 /*
@@ -137,12 +142,15 @@
       .dout({sop_o,eop_o,be_o[1:0],dataout}), // Bus [35 : 0] 
       .empty(empty),
       .full(Fifo_full),
-      .rd_data_count(), // Bus [11 : 0] 
+      .rd_data_count(occupied_sysclk), // Bus [11 : 0] 
       .wr_data_count(occupied)); // Bus [11 : 0] 
    
    assign         Fifo_space[15:RX_FF_DEPTH] = 0;
    assign         Fifo_space[RX_FF_DEPTH-1:0] = ~occupied;
-
+   assign         fifo_occupied = occupied_sysclk;
+   assign         fifo_full_dbg = Fifo_full;   // FIXME -- in wrong clock 
domain
+   assign         fifo_empty = empty;
+   
    // mac side fifo interface
    //   Input - Rx_mac_rd
    //   Output - Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err, 
Rx_mac_data, Rx_mac_BE

Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v   2008-08-01 02:27:42 UTC (rev 
9099)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v   2008-08-01 02:29:50 UTC (rev 
9100)
@@ -95,6 +95,10 @@
 output          Rx_apply_rmon           ,
 output  [2:0]   Rx_pkt_err_type_rmon    ,
 output  [2:0]   Rx_pkt_type_rmon        ,
+
+     output [15:0] rx_fifo_occupied,
+     output rx_fifo_full,
+     output rx_fifo_empty,
      output [31:0] debug
 );
 
//******************************************************************************
@@ -191,7 +195,11 @@
 .Rx_mac_BE                   (Rx_mac_BE                 ),
 .Rx_mac_sop                  (Rx_mac_sop                ), 
 .Rx_mac_eop                  (Rx_mac_eop                ),
-.Rx_mac_err                  (Rx_mac_err                )
+.Rx_mac_err                  (Rx_mac_err                ),
+
+.fifo_occupied(rx_fifo_occupied),
+.fifo_full_dbg(rx_fifo_full),
+.fifo_empty(rx_fifo_empty)
 ); 
 
    Broadcast_filter U_Broadcast_filter