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[Commit-gnuradio] r9103 - usrp2/trunk/fpga/serdes
From: |
matt |
Subject: |
[Commit-gnuradio] r9103 - usrp2/trunk/fpga/serdes |
Date: |
Thu, 31 Jul 2008 20:33:30 -0600 (MDT) |
Author: matt
Date: 2008-07-31 20:33:30 -0600 (Thu, 31 Jul 2008)
New Revision: 9103
Modified:
usrp2/trunk/fpga/serdes/serdes_fc_tx.v
Log:
removed clock domain crossing since that is now done in the receiver
Modified: usrp2/trunk/fpga/serdes/serdes_fc_tx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_fc_tx.v 2008-08-01 02:32:47 UTC (rev
9102)
+++ usrp2/trunk/fpga/serdes/serdes_fc_tx.v 2008-08-01 02:33:30 UTC (rev
9103)
@@ -2,38 +2,18 @@
module serdes_fc_tx
(input clk, input rst,
- input ser_rx_clk, input xon_rcvd, input xoff_rcvd, output reg inhibit_tx);
+ input xon_rcvd, input xoff_rcvd, output reg inhibit_tx);
// XOFF means stop sending, XON means start sending
-
- reg xon_d1, xon_d2, xoff_d1, xoff_d2;
- reg xon_ret, xon_ret_d1, xoff_ret, xoff_ret_d1;
+ // clock domain stuff happens elsewhere, everything here is on main clk
- // Make delayed copies in its own clock domain
- always @(posedge ser_rx_clk)
- begin
- xon_d1 <= xon_rcvd;
- xon_d2 <= xon_d1;
- xoff_d1 <= xoff_rcvd;
- xoff_d2 <= xoff_d1;
- end
-
- // Transfer copies to our clock domain, flop once for metastability purposes
- always @(posedge clk)
- begin
- xon_ret <= xon_rcvd | xon_d1 | xon_d2;
- xoff_ret <= xoff_rcvd | xoff_d1 | xoff_d2;
- xon_ret_d1 <= xon_ret;
- xoff_ret_d1 <= xoff_ret;
- end
-
reg [15:0] state;
always @(posedge clk)
if(rst)
state <= 0;
- else if(xoff_ret_d1)
+ else if(xoff_rcvd)
state <= 255;
- else if(xon_ret_d1)
+ else if(xon_rcvd)
state <= 0;
else if(state !=0)
state <= state - 1;
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