[Commit-gnuradio] r10771 - in gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top: . u2_rev3_iad

[jcorgan]

Author: jcorgan
Date: 2009-04-04 11:13:40 -0600 (Sat, 04 Apr 2009)
New Revision: 10771

Added:
   gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/
   gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
Log:
Copied project and receive pipeline for u2_rev3_iad


Property changes on: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad
___________________________________________________________________
Added: svn:ignore
   + build


Copied: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile 
(from rev 10770, 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3/Makefile)
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile   
                            (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile   
    2009-04-04 17:13:40 UTC (rev 10771)
@@ -0,0 +1,248 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v \
+top/u2_rev3_iad/dsp_core_rx.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+       @echo make proj, check, synth, bin, or clean
+
+proj:
+       PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)  
+
+check:
+       PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)      
+
+synth:
+       PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)  
+
+bin:
+       PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)         
+
+clean:
+       rm -rf $(BUILD_DIR)
+
+


Property changes on: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile
___________________________________________________________________
Added: svn:mergeinfo
   + 
/gnuradio/branches/developers/eb/t348/usrp2/fpga/top/u2_rev3/Makefile:10638-10648
/gnuradio/branches/developers/eb/t378/usrp2/fpga/top/u2_rev3/Makefile:10683-10688
/gnuradio/branches/developers/jblum/gui_guts/usrp2/fpga/top/u2_rev3/Makefile:10464-10658
/gnuradio/branches/developers/jblum/vlen/usrp2/fpga/top/u2_rev3/Makefile:10667-10677
/gnuradio/branches/developers/jcorgan/fw-optimize/usrp2/fpga/top/u2_rev3/Makefile:10428-10429
/gnuradio/branches/developers/jcorgan/gpio2/usrp2/fpga/top/u2_rev3/Makefile:10713-10765
/gnuradio/branches/developers/michaelld/am_swig_4/usrp2/fpga/top/u2_rev3/Makefile:10555-10595
/gnuradio/branches/developers/michaelld/two_mods/usrp2/fpga/top/u2_rev3/Makefile:10540-10546

Copied: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
 (from rev 10770, 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/sdr_lib/dsp_core_rx.v)
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
                          (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
  2009-04-04 17:13:40 UTC (rev 10771)
@@ -0,0 +1,179 @@
+
+`define DSP_CORE_RX_BASE 160
+module dsp_core_rx
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   input [15:0] io_rx,
+
+   output [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg [13:0] adc_i, adc_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [35:0] prod_i, prod_q;
+   wire [23:0] i_cordic, q_cordic;
+   wire [23:0] i_cic, q_cic;
+   wire [17:0] i_cic_scaled, q_cic_scaled;
+   wire [17:0] i_hb1, q_hb1;
+   wire [17:0] i_hb2, q_hb2;
+   wire [15:0] i_out, q_out;
+
+   wire        strobe_cic, strobe_hb1, strobe_hb2;
+   wire        enable_hb1, enable_hb2;
+   wire [7:0]  cic_decim_rate;
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+     
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+     
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+
+   wire [1:0] gpio_ena;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(gpio_ena),.changed());
+
+   // The TVRX connects to what is called adc_b, thus A and B are
+   // swapped throughout the design.
+   //
+   // In the interest of expediency and keeping the s/w sane, we just remap 
them here.
+   // The I & Q fields are mapped the same:
+   // 0 -> "the real A" (as determined by the TVRX)
+   // 1 -> "the real B"
+   // 2 -> const zero
+   
+   always @(posedge clk)
+     case(muxctrl[1:0])                // The I mapping
+       0: adc_i <= adc_b_ofs;  // "the real A"
+       1: adc_i <= adc_a_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])                // The Q mapping
+       0: adc_q <= adc_b_ofs;  // "the real A"
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+       
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
+   
+   cordic_z24 #(.bitwidth(24))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+           .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]),
+           .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   cic_strober 
cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
+                          .strobe_fast(1),.strobe_slow(strobe_cic) );
+
+   cic_decim #(.bw(24))
+     decim_i (.clock(clk),.reset(rst),.enable(run),
+             .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+             .signal_in(i_cordic),.signal_out(i_cic));
+   
+   cic_decim #(.bw(24))
+     decim_q (.clock(clk),.reset(rst),.enable(run),
+             .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+             .signal_in(q_cordic),.signal_out(q_cic));
+
+   round_reg #(.bits_in(24),.bits_out(18)) round_icic 
(.clk(clk),.in(i_cic),.out(i_cic_scaled));
+   round_reg #(.bits_in(24),.bits_out(18)) round_qcic 
(.clk(clk),.in(q_cic),.out(q_cic_scaled));
+   reg                strobe_cic_d1;
+   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
+   
+   small_hb_dec #(.WIDTH(18)) small_hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),
+      
.stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1));
+   
+   small_hb_dec #(.WIDTH(18)) small_hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),
+      
.stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
+
+   wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : 
{1'b0,cic_decim_rate};
+   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb),
+      
.stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
+
+   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb),
+      .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
+
+   round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
+   round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
+
+   // Streaming GPIO
+   //
+   // io_rx[15] => I channel LSB if gpio_ena[0] high
+   // io_rx[14] => Q channel LSB if gpio_ena[1] high
+
+   reg [31:0] sample_reg;
+   always @(posedge clk)
+     begin
+       sample_reg[31:17] <= i_out[15:1];
+       sample_reg[15:1]  <= q_out[15:1];
+       sample_reg[16]    <= gpio_ena[0] ? io_rx[15] : i_out[0]; 
+       sample_reg[0]     <= gpio_ena[1] ? io_rx[14] : q_out[0];
+     end
+   
+   assign      sample = sample_reg;
+   assign      strobe = strobe_hb2;
+   assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, 
strobe_cic_d1, strobe_hb1, strobe_hb2};
+   
+endmodule // dsp_core_rx


Property changes on: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
___________________________________________________________________
Added: svn:mergeinfo
   + 
/gnuradio/branches/developers/eb/t348/usrp2/fpga/sdr_lib/dsp_core_rx.v:10638-10648
/gnuradio/branches/developers/eb/t378/usrp2/fpga/sdr_lib/dsp_core_rx.v:10683-10688
/gnuradio/branches/developers/jblum/gui_guts/usrp2/fpga/sdr_lib/dsp_core_rx.v:10464-10658
/gnuradio/branches/developers/jblum/vlen/usrp2/fpga/sdr_lib/dsp_core_rx.v:10667-10677
/gnuradio/branches/developers/jcorgan/fw-optimize/usrp2/fpga/sdr_lib/dsp_core_rx.v:10428-10429
/gnuradio/branches/developers/jcorgan/gpio2/usrp2/fpga/sdr_lib/dsp_core_rx.v:10713-10765
/gnuradio/branches/developers/michaelld/am_swig_4/usrp2/fpga/sdr_lib/dsp_core_rx.v:10555-10595
/gnuradio/branches/developers/michaelld/two_mods/usrp2/fpga/sdr_lib/dsp_core_rx.v:10540-10546