[Commit-gnuradio] r10786 - gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad

[jcorgan]

Author: jcorgan
Date: 2009-04-06 20:19:38 -0600 (Mon, 06 Apr 2009)
New Revision: 10786

Added:
   gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/cmdfile
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
   gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/wave.sh
Modified:
   gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/
   gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile
Log:
Add skeleton RX path testbench


Property changes on: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad
___________________________________________________________________
Modified: svn:ignore
   - build

   + build
*.vcd
dsp_core_tb
*.dat


Modified: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile   
    2009-04-06 22:10:34 UTC (rev 10785)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile   
    2009-04-07 02:19:38 UTC (rev 10786)
@@ -228,7 +228,7 @@
 # Make Options
 ##################################################
 all:
-       @echo make proj, check, synth, bin, or clean
+       @echo make proj, check, synth, bin, testbench, or clean
 
 proj:
        PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)  
@@ -242,7 +242,11 @@
 bin:
        PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)         
 
+testbench:
+       iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v
+
 clean:
        rm -rf $(BUILD_DIR)
-
-
+       rm -f dsp_core_tb
+       rm -f *.lx2
+       rm -f *.dat

Added: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/cmdfile
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/cmdfile    
                            (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/cmdfile    
    2009-04-07 02:19:38 UTC (rev 10786)
@@ -0,0 +1,4 @@
+-y .
+-y ../../sdr_lib
+-y ../../control_lib
+-y ../../models

Added: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
                                (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
        2009-04-07 02:19:38 UTC (rev 10786)
@@ -0,0 +1,83 @@
+[size] 1680 975
+[pos] -1 -1
+*-20.692646 1008000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
+[treeopen] dsp_core_tb.
address@hidden
+-SYSCON
address@hidden
+dsp_core_tb.clk
+dsp_core_tb.rst
+dsp_core_tb.run
address@hidden
+-
+-Settings Bus
address@hidden
+dsp_core_tb.set_addr[7:0]
+dsp_core_tb.set_data[31:0]
address@hidden
+dsp_core_tb.set_stb
address@hidden
+-
+-ADC Interface
address@hidden
+dsp_core_tb.adc_a[13:0]
+dsp_core_tb.adc_b[13:0]
address@hidden
+-
+-DSP Output
address@hidden
+dsp_core_tb.sample[31:0]
address@hidden
+dsp_core_tb.stb
address@hidden
+-
+-
+-Rx Path Internals
address@hidden
+dsp_core_tb.rx_path.adc_a_ofs[13:0]
+dsp_core_tb.rx_path.adc_b_ofs[13:0]
+dsp_core_tb.rx_path.adc_i[13:0]
+dsp_core_tb.rx_path.adc_q[13:0]
+dsp_core_tb.rx_path.muxctrl[3:0]
+dsp_core_tb.rx_path.io_rx[15:0]
+dsp_core_tb.rx_path.scale_i[15:0]
+dsp_core_tb.rx_path.scale_q[15:0]
+dsp_core_tb.rx_path.prod_i[35:0]
+dsp_core_tb.rx_path.prod_q[35:0]
+dsp_core_tb.rx_path.cic_decim_rate[7:0]
address@hidden
+dsp_core_tb.rx_path.enable_hb1
+dsp_core_tb.rx_path.enable_hb2
address@hidden
+dsp_core_tb.rx_path.cpi_hb[8:0]
address@hidden
+dsp_core_tb.rx_path.strobe_cic
+dsp_core_tb.rx_path.strobe_cic_d1
address@hidden
+dsp_core_tb.rx_path.phase[31:0]
+dsp_core_tb.rx_path.phase_inc[31:0]
+dsp_core_tb.rx_path.i_cordic[23:0]
+dsp_core_tb.rx_path.q_cordic[23:0]
address@hidden
+dsp_core_tb.rx_path.gpio_ena[1:0]
address@hidden
+dsp_core_tb.rx_path.i_cic[23:0]
+dsp_core_tb.rx_path.q_cic[23:0]
+dsp_core_tb.rx_path.i_cic_scaled[17:0]
+dsp_core_tb.rx_path.q_cic_scaled[17:0]
address@hidden
+dsp_core_tb.rx_path.strobe_hb1
address@hidden
+dsp_core_tb.rx_path.i_hb1[17:0]
+dsp_core_tb.rx_path.q_hb1[17:0]
address@hidden
+dsp_core_tb.rx_path.strobe_hb2
address@hidden
+dsp_core_tb.rx_path.i_hb2[17:0]
+dsp_core_tb.rx_path.q_hb2[17:0]
+dsp_core_tb.rx_path.i_out[15:0]
+dsp_core_tb.rx_path.q_out[15:0]
+dsp_core_tb.rx_path.debug[31:0]
+dsp_core_tb.rx_path.sample_reg[31:0]
address@hidden
+dsp_core_tb.rx_path.strobe

Added: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
                          (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
  2009-04-07 02:19:38 UTC (rev 10786)
@@ -0,0 +1,129 @@
+`timescale 1ns / 100ps
+
+module dsp_core_tb;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Sim-wide wires/busses                                                       
  //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // System control bus
+   reg                clk;                initial clk = 1'b0;
+   reg                rst;                 initial rst = 1'b1;
+   
+   // Configuration bus
+   reg                set_stb;             initial set_stb = 1'b0;
+   reg          [7:0] set_addr;            initial set_addr = 8'b0;
+   reg         [31:0] set_data;            initial set_data = 32'b0;
+
+   // ADC input bus
+   reg  signed [13:0] adc_a;               initial adc_a = 14'd0;
+   reg  signed [13:0] adc_b;               initial adc_b = 14'd0;
+
+   // RX sample bus
+   reg                run;                 initial run = 1'b1;
+   wire        [31:0] sample;
+   wire               stb;
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation control                                                          
  //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // Set up output files
+   initial begin
+      $dumpfile("dsp_core_tb.vcd");
+      $dumpvars(0,dsp_core_tb);
+   end
+
+   // Update display every 10 us
+   always #10000 $monitor("Time in us ",$time/1000);
+
+   // Generate master clock 50% @ 100 MHz
+   always
+     #5 clk = ~clk;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Unit(s) under test                                                          
  //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // Make unisims happy
+   // glbl glbl();
+
+   dsp_core_rx rx_path
+     (.clk(clk),.rst(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(0'b0),
+      .adc_b(adc_b),.adc_ovf_b(0'b0),
+      .io_rx(16'b0),
+      .run(run),.sample(sample),.strobe(stb),
+      .debug() );
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation output/checking                                                  
  //
+///////////////////////////////////////////////////////////////////////////////////
+
+   integer rx_file;
+   
+   initial
+     rx_file = $fopen("rx.dat", "wb");
+   
+   always @(posedge clk)
+     begin
+       // Write RX sample I&Q in format Octave can load
+       if (stb)
+         begin
+            $fwrite(rx_file, sample[31:16]);
+            $fputc(32, rx_file);
+            $fwrite(rx_file, sample[15:0]);
+            $fputc(13, rx_file);
+         end
+     end
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Tasks                                                                       
  //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task power_on;
+     begin
+       @(posedge clk)
+         rst = #1 1'b1;
+       @(posedge clk)
+         rst = #1 1'b0;
+     end
+   endtask // power_on
+   
+   // Strobe configuration bus with addr, data
+   task write_cfg_register;
+      input [7:0]  regno;
+      input [31:0] value;
+      
+      begin
+        @(posedge clk);
+        set_addr <= regno;
+        set_data <= value;
+        set_stb  <= 1'b1;
+        @(posedge clk);
+        set_stb  <= 1'b0;
+      end
+   endtask // write_cfg_register
+
+///////////////////////////////////////////////////////////////////////////////////
+// Individual tests                                                            
  //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task test_rx;
+      #10000 $finish;
+   endtask // test_rx
+   
+      
+///////////////////////////////////////////////////////////////////////////////////
+// Top-level test                                                              
  //
+///////////////////////////////////////////////////////////////////////////////////
+
+   // Execute tests
+   initial
+     begin
+       power_on();
+       test_rx();
+     end
+
+endmodule // dsp_core_tb

Added: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/wave.sh
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/wave.sh    
                            (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/wave.sh    
    2009-04-07 02:19:38 UTC (rev 10786)
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+gtkwave dsp_core_tb.vcd dsp_core_tb.sav &


Property changes on: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/wave.sh
___________________________________________________________________
Added: svn:executable
   + *