Re: netlists

[Steven Rubin]

> and of course, all of the rest of the gates in the design. So, the 
> question is, how would I go about getting my Verilog code into Electric. I 
> suppose one option is for me to write a program to manipulate the netlist 
> output of Icarus Verilog so that the netlist format is acceptable to 
> Electric so I can attempt to boot-strap my understanding to the next level.
>
> Perhaps, there allready exists either a Verilog compiler that has an 
> output compatible with Electrics input (please dont say Synopsis, Cadence, 
> or Mentor Graphics as I dont have any sheckles for this project other then 
> my weekend time). Or there is some translator that simplifies this issue.
>
> Anyone have any suggestions or comments.

As far as I know, there is no Verilog compiler that produces any of the 
Electric netlist formats.  And, of course, there is only 1 format of 
interest to you: the QUISC netlist format which the silicon compiler 
uses.  I think that it would be easier to write a program to convert some 
other netlist format (any that you may have) into QUISC.  After all, such 
netlists are merely components and connections.  It might even be simplest 
to modify Icarus Verilog to produce the correct netlist.

There are people who are investigating the integration of Icarus Verilot 
into Electric.  If this were to happen, they would certainly be interested 
in making it produce netlists that Electric can use.  If you are interested 
in such work, let me know.

   -Steven Rubin