RE: [Discuss-gnuradio] The ultimate SDR (Ethernet v. gigabit)

[Ettus, Matt]

> -----Original Message-----
> From: Steve Schear [mailto:address@hidden
> 
> Although I've never put together a kit I have managed several 
> projects, 
> including wireless to market.  I doubt there is very much 
> money to be made 
> on this sort of venture but it could be lots of fun and interesting 
> professionally.  I'd like to work with you and anyone else we 
> can find to 
> identify the design requirements and get this to going.


Great.  So far you [Steve] and Eric Blossom seem to be interested in the
effort.  Why don't we get started brainstorming features?  My idea of the
ultimate SDR would include:

- Everything controlled off of one 10MHz master oscillator input
- Modular Architecture
        - Master controller and 100Mbit ethernet interface
                - Multiple samplerate and resolution capable
                - Future upgradeable to Gbit ethernet
        - DSP Board
                - Digital Up and Down Conversion   baseband <--> common IF
        - RF Board
                - Full Duplex capable on independent bands (i.e. L and S
band simultaneously)
                - Up/Downconvert to common IF
                - Control signals for external LNA/PA and switching
        - Different RF boards for different frequency ranges
        - Different DSP boards (or multiple of the same type?) to allow for
multi-channel designs
        - Is the common IF interface between RF and DSP boards digital or
analog?
- Good Linux drivers and generic API for interfacing

Anything to add?  Somebody mentioned multiple channels.  Did that refer to
multiple signals from/to the same antenna or processing streams from
multiple antennas?   I'm interested in both.  I'm not sure if we should have
one SDR box capable of handling multiple antennas, or if we should just have
multiple SDR boxes in those cases.  If so, we'd need a way to synchronize
them, but that shouldn't be too hard.

The Opencores project Ethernet core seems to be working, and they are
gettting it to work with their OR1200 CPU!  Everything on the same FPGA,
with just an external PHY chip.  They use the Wishbone bus, so the CPU,
Ethernet core, RAM controller, and generic IO are all on the same bus.
There's even a gcc toolchain for it.  They've done some great work, and I
think it would be cool to use it, although I'm not wedded to it.  I do like
the idea of soft cores for everything so we don't have supplier problems on
microprocessors and specialized chips.

Comments?

Matt