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Re: [Discuss-gnuradio] Cheap ADC at 35MHz

From: Adrian Godwin
Subject: Re: [Discuss-gnuradio] Cheap ADC at 35MHz
Date: Wed, 17 Apr 2002 23:44:54 +0100

Marius Hauki wrote:
> Hi Adrian,
> does the chip have a separate input for the
> sync tip sample input ? If it has, might it be possible
> to hardwire this input to a fixed DC value via a decoupled
> potmeter ?

This is what the Bt848 datasheet says (the 878 might be different)

"A/D Clamping    

  An internally generated clamp control signal is used to clamp
  the inputs of the A/D converter for DC restoration of the video 
  signals. Clamping for both the YIN and CIN analog inputs occurs 
  within the horizontal sync tip. The YIN input is always restored 
  to ground while the CIN input is always restored to CLEVEL. 
  CLEVEL must be set with an external resistor network so that 
  it is biased to the midpoint between CREF­ and CREF+. External 
  clamping is not required because internal clamping is automatically 

I don't know what clamp value will be present if no signal is
ever present, so I assume it's necessary to provide one at some
time. Ideally, this should occur at the point during which the
input goes to its lowest possible value, as the clamped signal
will be translated to zero. Given that the sync detector is
looking for TV-like sync, this is hard to arrange unless we
deliberately superimpose a sync pattern (or provide one to
the sync input, which is separate from the video input) and
clip the video input at the same point.

In the test I did with the VBI capture, it's apparent that
the negative half-cycles are missing. This is presumably
because the clamping has operated with the input at an
average value in the middle of the AC signal, and so only
the positive half-cycles generate useful data.

It may not be necessary to continually generate sync
events : perhaps when the capture starts a few cycles 
of video-like signal could be used to  train the clamp,
and it could then be left alone.

There's also an AGC system which continuously averages
the high points of the input and generates a voltage
that defines the ADC maximum value. However, ths is 
fed back externally (again, the 878 might differ) so
can be fooled fairly easily.


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