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[Discuss-gnuradio] USRP update, etc
[Discuss-gnuradio] USRP update, etc
Wed, 17 Dec 2003 23:37:32 -0800
Savannah / Subversions is still down. There's information about its
status at http://savannah.gnu.org
The good news is that we're sending a few USRPs out in the next couple
of days. We've been in touch with you if one's coming your way. We
didn't have enough to get to everyone who expressed interest, but we
haven't forgotten you. Below is the "Getting Started" information. It
includes links to the code, schematics, etc.
See wiki http://comsec.com/wiki?UsrpProtos for ongoing updates.
Best wishes for the holiday season,
I wanted to let you know that Matt will be sending out your USRP's in
the next couple of days. They're working pretty well right now.
You will need some kind of USB 2.0 interface on your machine. We've
tested a few PCMCIA cards, and they work, but the throughput is about
25% of what I see on my ibm labtop.
The good news is that with a decent host controller we can sustain
31.25 MB/sec either reading or writing, and 1/2 that in each direction
if we are simultaneously reading and writing.
You'll need to download a couple of pieces of code to make it work.
The usrp code lives in a CVS repository on source forge. This
includes the firmware, the verilog for the fpga, and the host side
cvs -d:pserver:address@hidden:/cvsroot/opensdr login
cvs -z3 -d:pserver:address@hidden:/cvsroot/opensdr co -P usrp
The GNU Radio portion of the code would be in the FSF CVS repository
on subversions.gnu.org if it were up, but they're still in the middle
of a (very long) security audit after a root compromise.
In the mean while, you can grab a copy of the tarball at:
Take a look at
http://comsec.com/usrp for other goodies.
You'll find the schematic as well as the FPGA bitstream
(usrp_fpga.rbf) that we're using. You could generate it from the
verilog in usrp/fpga using the free beer tools from Altera if you're
so inclined. In any event, copy usrp_fpga.rbf to
To build the firmware, you'll need a recent snap shot of the SDCC 8051 C
compiler. You can find that at sdcc.sourceforge.net
Build the usrp tree first. It's the standard drill:
It's default prefix is /usr/local, please leave it that way since
there's still additional autoconf hacking required to get the right
paths compiled in to the library that loads the firmware.
It will put the compiled firmware in /usr/local/share/usrp/usrp_firmware.ihx
The host side libs and includes will be in /usr/local/lib and
/usr/local/include as usual.
Then build the GNU Radio tarball:
Once everything is built you can start checking the board out.
Start usbview and cable up the board. It should show up as an
"Unknown Device" with a vendor ID of 0xfffe.
Try running usrp/apps/test_usrp
This will load firmware and the fpga bistream into the board
and send a sine wave out the D/A's. By default it'll try running at
31.25 MB/sec. If you get messages about "Tx overruns" you'll need to
jack around with the -I <int-power-of-2> command line parameter to alter the
default interpolator rate.
Likewise test_usrp -i will test the input path. The -D <int-power-of-2>
flag controls the decimation rate.
After test_usrp loads the firmware, usbview should ID the device as a
"USRP proto rev 0", and squinting at the details will show that the
device implements 3 interfaces. They are (1) command and status, (2)
Tx path, (3) Rx path.
You may also want to mess around with usrp/apps/usrper. It will
twiddle all kinds of low level stuff on the board. Take a look at the
On the gnuradio front, we've been doing our experimentation using the
python interface. This stuff will probably get moved around in the
tree to better organize it, but in the mean while, take a look in
Programs of interest are:
tx_am.py misnamed (generates output)
foo2.py generate output.
The code is pretty straight forward.
Things to know about the USRP is that on the Tx path you've got these
controls (see usrp.h for the header and brief docs).
set_interp_rate (unsigned int rate) // 8,16,32,64,128,256
set_tx_freq (int channel, double freq)
Likewise, the Rx path has these:
set_adc_clk_div (unsigned int rate) // 2 <= rate <= 6
set_decim_rate (unsigned int rate) // 8,16,32,64,128,256
set_rx_freq (int channel, double freq)
The master clock on the USRP is 125e6. The DAC's and the FPGA signal
processing run at that rate. The ADC's run at 125e6 / adc_clk_div.
(FWIW, the final boards will have a 120 MHz master osc.)
The current fpga bitstream is only controlling two DAC's and two ADC's.
The connectors are as follows:
X308 and X309 are DAC outputs
X204 and X205 are ADC inputs
The two ADC's feed the I & Q inputs of one digital down converter,
the output of which are interleaved shorts of I & Q. Those shorts are
send across the USB.
On the transmit path, 16-bit interleaved I & Q data goes across the
USB and into the digital up converter. The upconverted signal is sent
to the DACs, I on one and Q on the other.
I'm sure I'm leaving tons of information out.
Feel free to discuss all this on the main GNU Radio list and to work
up some wiki pages linked from http://comsec.com/wiki?UsrpProtos
- [Discuss-gnuradio] USRP update, etc,
Eric Blossom <=