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[Discuss-gnuradio] Re: measuring latency, etc

From: Eric Blossom
Subject: [Discuss-gnuradio] Re: measuring latency, etc
Date: Wed, 16 Mar 2005 15:47:32 -0800
User-agent: Mutt/1.5.6i

On Wed, Mar 16, 2005 at 01:47:20PM -0800, Javs wrote:
> Eric, 
> Now I am curious to measure it myself. I looked at the usrper.cc
> code and want to see how much time it takes to read/ write from/to
> the FPGA.

> specifically :
> /*
>  * diagnostic routine.  This requires that the
>  * passthru bitsteam is loaded into the fpga.
>  *
>  * We reset the fpga, disable tx, then send a single packet
>  * with known contents.  After waiting for user input,
>  * we enable tx, which should send the know data to the dac port
>  * which we can watch with the logic analyzer.
>  */
> Could you elabourate this please. if possible with an example ? 

> Also what possible values can "reg8" and "value 32" can take in the
> function "write_fpga_reg <reg8> <value32>"?

usrper is not the tool you want to be using.  It is incapable of high
speed streaming access to the USRP.  Generally speaking you *really*
don't want to be programming at this level.  Use the usrp_standard.h
interface.  The valid registers and their values depends on the fpga
configuration loaded and are subject to change at a whim.  Also,
writing the FPGA registers is relatively slow.  We bit bang the data
over a serial bus from the FX2.  The latency that matters in most
cases is the time to get the streaming I&Q data pushed around.

Here's an easy way to measure round trip latency:

  Hook up a signal generator to one of the Rx basic inputs and to one
  input of an oscilloscope.  Hook up one Tx basic output to
  another input on the o'scope.

  Write some code on the host that reads from usrp.source_c and writes
  to usrp.sink_c

  Look at the delay between the two traces on your o'scope.

> Once i transfer the data, Can I measure the data on the FPGA with
> the logic analyzer ? 

This is possible.  You'd have to build a custom fpga bitstream that
outputs the debugging info you're interested in on one or more of the
basic daughterboard headers. Take a look at usrp_std/usrp_std.v and
the DEBUG_OWNS_IO_PINS define.

Please note that if you're cooking your own FPGA code, you need to be
especially careful not to fry the board.  It you leave the bus
interfaces alone and are careful not to drive the d'board i/o pins
inappropriately you're probably reasonably safe.


Note, I've started cc:ing the list since this dialog may be of
interest to others.

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