Re: [Discuss-gnuradio] USRP DDC usage

[Krzysztof Kamieniecki]

Quoting Achilleas Anastasopoulos <address@hidden>:
> I have a question/observation on this issue:
> 
> Since the DDC multiplication is complex and since the internal DDC 
> oscilator is noncoherent, I do not see a difference between the MUX 
> settings: 0x33221100 and 0xf3f2f1f0.
> 
Is the difference between them a phase shift of 45 degrees and a gain ratio of
sqrt(2)?

> Similarly, with the setting 0x00003210 you will never be able to
> separate the two channels coming from ADC0/ADC1 and ADC2/ADC3.
> 
You can seperate ADC0/ADC1 and ADC2/ADC3 if you set the DDC frequency to zero (I
think you also have to never have set it to a non-zero value after powerup,
since you can't reset the DDC phase)

> Is this right?
> 
> Thanks
> Achilleas
> 
> 
> 
> 
> 
> On Wed, May 25, 2005 at 02:54:05PM -0400, Philip Balister wrote:
> 
>  >> I'm working on making a SCA component for the usrp based on the usrp
>  >> standard interface. I've got a few questions on how to use the DDC's and
>  >> the input mux.
>  >>
>  >> If I set the mux word to 0x33221100 (and the number of channels to four)
>  >> I believe I will have 4 channels of complex data from each A2D.
> 
> 
> FYI, the current fpga image only support two DDCs.
> 
> You always get complex data out of the DDCs.  The question is what are
> you putting in?
> 
> If you want two DDCs with a different pair of A/Ds to each one
> the mux should == 0x00003210
> 
> 
>  >> If I set the mux word to 0xf3f2f1f0 I will have four channels of real
>  >> data, interleaved with the zeros from the Q channel.
> 
> 
> Yes.  This will feed a zero to the Q input of each DDC and will feed
> ADC's 3, 2, 1, 0 to the I inputs.  Note that there are only two
> channels available in the current FPGA build.
> 
> Eric
> 
> 
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