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Re: [Discuss-gnuradio] Where is the output enabled of rx reference clock

From: Martin Dvh
Subject: Re: [Discuss-gnuradio] Where is the output enabled of rx reference clock for dbsrx
Date: Tue, 25 Oct 2005 20:09:00 +0200
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.5b) Gecko/20030823

Eric Blossom wrote:
On Tue, Oct 25, 2005 at 02:44:51AM +0200, Martin Dvh wrote:

I want to enable sync input and output pins and are looking for where the these should be set. In my search for examples, I looked for the place where the output is enabled for the 4Mhz reference clock, which is output on io[0] for some daughterboards, like the dbsrx.

But I can't seem to find where this output is enabled.

Secret's revealed!!

The daughterboard handling code sets it.
See db_flexrf.py for example usage.  Search for refclk

From fpga_regs_standard.h:

// Control whether a reference clock is sent to the daughterboards,
// and what frequency
// Bit 7  -- 1 turns on refclk, 0 allows IO use
// Bits 6:0 Divider value

#define FR_TX_A_REFCLK          40
#define FR_RX_A_REFCLK          41
#define FR_TX_B_REFCLK          42
#define FR_RX_B_REFCLK          43

We really ought to machine generate the python equivalent. We already generate a verilog equivalent.
Can't swig do this for us?


Thanks, Eric, now I found where the output is enabled.
I didn't notice the following line:

I already found the FR_RX_A_REFCLK register but this only enables the refclk 
signal, not the actual output.

For db_dbs_rx.py I suggest to move
Which is now in the beginning of the init function of dbs_rx

To within the _enable_refclk function.
def _enable_refclk(self,enable):

(See attched minipatch)

Or even do as suggested in the FIXME comment in db_flexrf.py
        # FIXME this belongs in base class
        # set refclk freq and turn it on

--- dbs_rx.py   Tue Jun 14 06:11:51 2005
+++ dbs_rx_mdvh.py      Tue Oct 25 19:58:02 2005
@@ -65,7 +65,6 @@
         # sets _u and _which
         daughterboard_base.base.__init__(self, usrp, which)
-        self._u._write_oe(self._which,0x0001,0x0001)
         #self._u.set_adc_buffer_bypass(self._which, True)
         self.i2c_addr = (0x67, 0x65)[self._which]
         # set basic parameters
@@ -100,8 +99,10 @@
                                    ((self.refclk_divisor & REFCLK_DIVISOR_MASK)
                                     | REFCLK_ENABLE))
+            self._u._write_oe(self._which,0x0001,0x0001)
             self._u._write_fpga_reg(self.refclk_reg, 0)
+            self._u._write_oe(self._which,0x0001,0x0000)
     def _write_reg (self, regno, v):
         """regno is in [0,5], v is value to write to register"""

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