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Re: [Discuss-gnuradio] grGPS Preliminary Schematic

From: David Bengtson
Subject: Re: [Discuss-gnuradio] grGPS Preliminary Schematic
Date: Thu, 06 Apr 2006 18:55:01 -0400
User-agent: Thunderbird 1.5 (Windows/20051201)

Clark Pope wrote:
I guess I missed the answer to why you can't do GPS with the DBS board? It has the hooks to apply power to the antenna and it certainly has the bandwidth and tuning range. If you're concerned about having a nice clock rate to make the despreading easier you can replace the oscillator on your USRP with a 32.768MHz oscillator, for example. (I'm in the process of switching mine to 44 MHz ro make wlan easier.)


You may well be able to do it with the DBS board. However, GPS is a pretty weak signal, and I suspect that the noise figure is too high.

Also, there is a good sized population of college students doing GPS work, so I thought that building a GPS specific board would be useful for those folks.

From: David Bengtson <address@hidden>
Reply-To: address@hidden
To: Martin Dvh <address@hidden>
CC: address@hidden, gnuradio mailing list <address@hidden>
Subject: Re: [Discuss-gnuradio] grGPS Preliminary Schematic
Date: Thu, 06 Apr 2006 06:18:49 -0400

Martin Dvh wrote:
David Bengtson wrote:
After far to long, I've updated the information on the Gnu Radio GPS
board. I've finished a preliminary schematic, and I'd appreciate any
comments that anyone might have.
Why don't you use the usrp to generate your 16.384 or 32.768 MHz refclock. Most daugterboards (except the tvrx) use this feature (They all use a 4Mhz refclock on io pin 0.
The only difference with your design is that you need another frequency.
The cyclone fpga in the usrp has internal PLLs which can generate all kinds of frequencies.
(They are not used at the moment)

(Sorry, there is a typo, the reference frequencies are 16.368/32.736 MHz)
That might work. 16.368 MHz/4 MHz is 1023/250, or a comparison frequency of 16 kHz. From a frequency generation point of view, I could probably get the right frequency from the USRP. I'm concerned about jitter and noise on that line though. The reference is used directly for the comparison frequency in the on-chip PLL, to generate a LO that is 1571.328 MHz. A 16 kHz spurious on this would really cause problems.

Because of this, I'd like to use a a clean reference clock for the reference. I could change the layout to bring a signal over from the connector to the reference input to check that though. That would make it possible to try this approach.

Re-Using the reference clock is why I brought the buffered clock signal over to the connector, so that it will be available to the FPGA.


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