Hello, There is something that's unclear to me about recompiling the verilog code. The way I did it before was to create a project, add to it the top level module usrp_std.v and all the modules in the sdr_lib file. Then at every compile, the compiler complains and ask for such or such verilog module, so I just look for that module in the ...usrp\fpga folder and add it to the project. I keep on adding the missing verilog files until I am able to fully compile the project. The only problem with this is that sometimes the compiler would say for example that I am missing the fifo_4k.v module. So I would look for that file in the folder I mentioned previously, but there are 2 such files. One of them is in the fpga\megacells folder and the other one is in the fpga\module folder. In such cases I am not sure which file to pick. I actually picked the one in the megacells folder and I was able to compile the project.
Any clarification on this matter? Which file should I pick in that case? Is there an easier way to recompile the verilog code?
I noticed there is a project file usrp_std.qpf in the usrp\fpga\toplevel\usrp_std folder but when I opened that file with Quartus II
6.0, it said that the file was previously opened with an older version of Quartus II. That is why I created a new project and added all the files manually.