[Discuss-gnuradio] Fewer than 8 bits per sample FPGA support

[Peter Monta]

> So the attached patch changes to round-to-nearest-even.

After thinking a bit, this is wrong: the proper (re-)quantizer is
just the MSBs of the original sample---one wants a mid-riser
quantizer to use the even number of output levels symmetrically.

Revised patch attached (still untested).

Cheers,
Peter Monta

--- rx_buffer.v.orig    2007-02-25 14:32:58.000000000 -0800
+++ rx_buffer.v 2007-03-01 02:57:00.000000000 -0800
@@ -51,8 +51,7 @@
     output [15:0] debugbus
     );
 
-   wire [15:0] fifodata, fifodata_8;
-   reg [15:0]  fifodata_16;
+   reg [15:0] fifodata;
    
    wire [11:0] rxfifolevel;
    wire rx_empty, rx_full;
@@ -96,60 +95,51 @@
        store_next <= #1 4'd0;
      else if(~rx_full & (bitwidth == 5'd8) & (store_next == (channels>>1)))
        store_next <= #1 4'd0;
+     else if(~rx_full & (bitwidth == 5'd4) & (store_next == (channels>>2)))
+       store_next <= #1 4'd0;
+     else if(~rx_full & (bitwidth == 5'd2))
+       store_next <= #1 4'd0;
+     else if(~rx_full & (bitwidth == 5'd1))
+       store_next <= #1 4'd0;
      else if(~rx_full & (store_next != 0))
        store_next <= #1 store_next + 4'd1;
 
-   assign    fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
+   wire [7:0] onebit_vector = 
{ch_0[15],ch_1[15],ch_2[15],ch_3[15],ch_4[15],ch_5[15],ch_6[15],ch_7[15]};
+   reg [7:0] onebit_saved;
+   reg onebit_flag;
 
-   assign    fifodata_8 = {round_8(top),round_8(bottom)};
-   reg [15:0] top,bottom;
-
-   function [7:0] round_8;
-      input [15:0] in_val;
+   always @(posedge rxclk)
+     if(reset)
+       onebit_flag <= #1 0;
+     else if(rxstrobe & (store_next == 0))
+       onebit_flag <= #1 ~onebit_flag;
+     else if(~rx_full & (bitwidth == 5'd1))
+       onebit_saved <= #1 onebit_vector;
 
-      round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
-   endfunction // round_8
-      
-   always @*
-     case(store_next)
-       4'd1 : begin
-         bottom = ch_0;
-         top = ch_1;
-       end
-       4'd2 : begin
-         bottom = ch_2;
-         top = ch_3;
-       end
-       4'd3 : begin
-         bottom = ch_4;
-         top = ch_5;
-       end
-       4'd4 : begin
-         bottom = ch_6;
-         top = ch_7;
-       end
-       default : begin
-         top = 16'hFFFF;
-         bottom = 16'hFFFF;
-       end
-     endcase // case(store_next)
-   
    always @*
-     case(store_next)
-       4'd1 : fifodata_16 = ch_0;
-       4'd2 : fifodata_16 = ch_1;
-       4'd3 : fifodata_16 = ch_2;
-       4'd4 : fifodata_16 = ch_3;
-       4'd5 : fifodata_16 = ch_4;
-       4'd6 : fifodata_16 = ch_5;
-       4'd7 : fifodata_16 = ch_6;
-       4'd8 : fifodata_16 = ch_7;
-       default : fifodata_16 = 16'hFFFF;
-     endcase // case(store_next)
-   
+     case({bitwidth,store_next})
+       {5'd16,4'd1} : fifodata = ch_0;
+       {5'd16,4'd2} : fifodata = ch_1;
+       {5'd16,4'd3} : fifodata = ch_2;
+       {5'd16,4'd4} : fifodata = ch_3;
+       {5'd16,4'd5} : fifodata = ch_4;
+       {5'd16,4'd6} : fifodata = ch_5;
+       {5'd16,4'd7} : fifodata = ch_6;
+       {5'd16,4'd8} : fifodata = ch_7;
+       {5'd8,4'd1} : fifodata = {ch_0[15:8],ch_1[15:8]};
+       {5'd8,4'd2} : fifodata = {ch_2[15:8],ch_3[15:8]};
+       {5'd8,4'd3} : fifodata = {ch_4[15:8],ch_5[15:8]};
+       {5'd8,4'd4} : fifodata = {ch_6[15:8],ch_7[15:8]};
+       {5'd4,4'd1} : fifodata = {ch_0[11:8],ch_1[11:8],ch_2[11:8],ch_3[11:8]};
+       {5'd4,4'd2} : fifodata = {ch_4[11:8],ch_5[11:8],ch_6[11:8],ch_7[11:8]};
+       {5'd2,4'd1} : fifodata = 
{ch_0[9:8],ch_1[9:8],ch_2[9:8],ch_3[9:8],ch_4[9:8],ch_5[9:8],ch_6[9:8],ch_7[9:8]};
+       {5'd1,4'd1} : fifodata = {onebit_saved,onebit_vector};
+       default : fifodata = 16'hFFFF;
+     endcase
+
    fifo_4k rxfifo 
      ( .data ( fifodata ),
-       .wrreq (~rx_full & (store_next != 0)),
+       .wrreq (~rx_full & ( (bitwidth==5'd1) ? (onebit_flag && (store_next != 
0)) : (store_next != 0) )),
        .wrclk ( rxclk ),
 
        .q ( usbdata ),