On 6/28/07, Trond Danielsen <address@hidden> wrote:
> Hi,
>
> after having read several papers on the subject, I am still not able
> to find the answer I am looking for. I wonder how to calculate the
> frequency resolution of the CORDIC algorithm. In an earlier post to
> this mailing list it was stated that the resolution is approximately
> 0.01 Hz. Could anyone point me to where I can find a deviation of this
> result?
This paper is really good for understanding the CORDIC:
http://web.njit.edu/~hkj2/CORDIC.pdf
It is specifically written to look at FPGA implementations, which is nice.
As I understand it, the USRP uses the CORDIC as described in section
3.1 of that paper. A phase accumulator is used to spin the angle
around, and the modulated sin/cos or xi is the output on xo and yo
after 12 iterations of the algorithm. The value of zo should be zero,
and any error leftover should be represented on that output.
The resolution should really be how slowly you can spin the zi
component while maintaining accuracy out of the CORDIC. It may be
that with 12 iterations and 16-bit inputs 0.01 Hz is possible, whereas
more iterations or larger inputs might get better resolution, but I
suspect you're really past the point of diminishing returns at that
point.
Is that helpful?