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Re: [Discuss-gnuradio] Running a Test Simulation of FPGA Code with Quart


From: Brian Padalino
Subject: Re: [Discuss-gnuradio] Running a Test Simulation of FPGA Code with Quartus
Date: Tue, 7 Aug 2007 16:52:20 -0400

On 8/7/07, Reid N Kleckner <address@hidden> wrote:
> Hello,
>
> I've written a small Verilog module for the FPGA on the USRP to do phase
> recovery.  I'd like to test it in isolation before I try it out on the board,
> but I'm having major problems feeding Quartus two 16 bit sine and cosine
> signals with a random phase offset.  The idea is that q_out after the phase
> locked loop should be zero for this case, and noise for a real signal.  It
> seems that the only tools for generating signals within Quartus basically let
> you manually specify integer levels for bit vectors and a bunch of other 
> things
> for single bit wires.

Verilog has a real type that is not synthesizable, but useful for
testbenches.  I have written a copy of the ieee.math_real package from
VHDL for VHDL.  It is not very fast, but it works pretty nicely.

It's available in zhuochen's developer directory here:
    
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test/math_real.v

I used it in the testbench here to create some sines and cosines:
    
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test/test_chan_fifo_reader.v

Let me know if you find it useful or have problems with it.  Also note
that if you plan on using it with Icarus Verilog that you need one of
the latest developer snapshots as the code I wrote found some problems
in their real value handling.

It is definitely NOT recommended you just put it into an FPGA and run
with it as you really have no idea what's going on inside there.
Accurate modeling can really help with your debugging time.

Brian




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