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Re: [Discuss-gnuradio] rssi questions

From: George Nychis
Subject: Re: [Discuss-gnuradio] rssi questions
Date: Tue, 07 Aug 2007 20:00:36 -0400
User-agent: Thunderbird (X11/20070604)

Johnathan Corgan wrote:
Brian Padalino wrote:

I haven't taken a look at the daughterboards, but do they all use different amplifiers and different numbers of stages?

They are mostly different.  All the RFX boards are similar, but the RFX
uses a different front end from the TVRX, DBSRX and the new boards still
in development.

Are the amplifiers setup in a linear or logarithmic mode?  Do they
change significantly between the boards, or could a generic AGC
module be created?

I think you could create a generic "rx power estimator" module on the
FPGA that used the ADC output and some configuration registers that were
poked at by the host code when the daughterboards are configured.  From
the host point of view this doesn't add much value, as you could more
easily just do the same calculations on the host.  If you need the value
as part of an AGC loop, though, obtaining it on the FPGA is needed for
tight control.

(I haven't looked into controlling the RFX board gain from the FPGA.
Matt is better to answer this one.)

Thanks for all the responses and info on the RSSI. I'm following most of it, but will probably have a bunch more questions the further we get in to it.

The reason we are poking at this is because we are interested in using it for carrier sense. I agree that reporting it in terms of dB would be nice. I guess theres a tradeoff here of complexity/power at the FPGA which we can discuss. But you're saying that given information in registers from the daughterboard setup, it is possible?

Doing the calculations on the FPGA would give us much tighter control, this is kind of what I was tossing up for discussion in my carrier sense thread. If the host does the RSSI calculation, there is a delay of essentially a round trip to the USRP:
- time for an incoming packet to carry the RSSI to the host
- time to calculate RSSI, make decision, and push back down to USRP

If we calculate the RSSI in the FPGA, we can mark a packet and specify that we want to carrier sense before its transmission. The FPGA could compute the RSSI, wait for the carrier to go below some threshold for a given amount of time, and then toss the packet out or transmit.

- George

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