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[Discuss-gnuradio] Re: Changing interp rate dynamically?

From: Michael Dickens
Subject: [Discuss-gnuradio] Re: Changing interp rate dynamically?
Date: Wed, 10 Oct 2007 09:27:44 -0400

Revisiting this topic, since it's been 3 weeks and I've heard back nothing ... which probably means that everyone is too busy trying to get release 3.1 out the door to deal with this issue? Should I just enter this as a bug to be fixed?

My original observation is that the USRP's TX interp rate doesn't seem to work when changed dynamically. Brian and Eric and others replied back that the FPGA code looks OK, but that it's never really been tested for that purpose (the RX decim does work, and has been tested). I have followed the TX path in software to the point where data is transferred to the USRP, and the data looks OK to that point. It is possible that the USB transport is messing with the data, but I think that's unlikely. It's much more likely that the FPGA code has a bug. Unfortunately I do not "do" FPGA code yet, though I'm trying to learn, so I can't debug past where the data leaves the host computer.

Thus I created a -very- simple python script to test this issue. My example code creates a sig_source with sinusoid and connects that to a USRP sink, set to 455 MHz at maximum gain and a given interp_rate. It starts the TB/FG running, then sleeps for 15 seconds. It sets up a USRP for TX at a given interp_rate, then starts the FG running (which will be a separate thread) and sleeps for 15 seconds. It then resets the interp_rate to -the same value-, and waits for the FG to finish (via user-interrupt).

I simultaneously run a waterfall scope on another computer, and can see the sinusoid as a "vertical line" on the scope (which is as expected). After 15 seconds, the code sets the interp rate to the - same value- as before, and the waterfall scope changes dramatically ... most of the energy is "near" DC, but it looks somewhat like a time-sinusoid-modulated frequency-sinc.

Something is going on with the TX interp rate, most likely on the FPGA in my experimenting thus far (and/or: tell me what I'm doing incorrectly in my python script). Please try out the example script, and see for yourselves. - MLD

Attachment: test_usrp_interp.py
Description: Text Data

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