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[Discuss-gnuradio] Re: Help with RA please


From: David
Subject: [Discuss-gnuradio] Re: Help with RA please
Date: Fri, 30 Nov 2007 19:07:39 -0500
User-agent: Thunderbird 2.0.0.9 (X11/20071115)

Anthony, you need to download and install Pyephem. You can get it here: http://rhodesmill.org/pyephem/

Sorry, I am not familiar with Ubuntu, so I can't help with installing it. But others on this list can help with that.
Dave


Message: 1
Date: Fri, 30 Nov 2007 17:40:55 +0000 (UTC)
From: "address@hidden" <address@hidden>
Subject: [Discuss-gnuradio] Help with RA please
To: address@hidden
Message-ID: <address@hidden>
Content-Type: text/plain;charset="UTF-8"


Hi,

I am running UBUNTU 7.10 and gnuradio-3.1.1. for USRP. The fm radio works fine. However, when I try running radio astronomy I receive the following. Can someone help please.

Thank you,

Frank
England

address@hidden:~/gnuradio/gr-radio-astronomy/src/python$ .
/usrp_ra_receiver.py

Traceback (most recent call last):
File "./usrp_ra_receiver.py", line 28, in <module>
from gnuradio.wxgui import stdgui2, ra_fftsink, ra_stripchartsink, ra_waterfallsink, form, slider, waterfallsink
File "/usr/local/lib/python2.5/site-
packages/gnuradio/wxgui/ra_stripchartsink.py", line 30, in <module>
    import ephem
ImportError: No module named ephem





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Message: 2
Date: Fri, 30 Nov 2007 12:58:38 -0500
From: "Marcus Leech" <address@hidden>
Subject: Re: [Discuss-gnuradio] Help with RA please
To: "address@hidden" <address@hidden>
Cc: address@hidden
Message-ID: <address@hidden>
Content-Type: text/plain; charset="utf-8"

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Message: 3
Date: Fri, 30 Nov 2007 17:01:01 -0500
From: "Ronald Jetli" <address@hidden>
Subject: [Discuss-gnuradio] Re: tx_chain - Verilog question
To: address@hidden
Message-ID:
        <address@hidden>
Content-Type: text/plain; charset="iso-8859-1"

Hi,

I do understand that there are "always" statements in the base code and the
flow of those base code is clear to me.

It is just this top module, whose logic is not clear to me. I tried writing
a test bench, but that didnt help either.

It would be great if anyone could spare a minute and throw some light ?

Hoping for some answers !

Thanks once again.

jetli.


On Nov 30, 2007 1:40 AM, Ronald Jetli <address@hidden> wrote:

Hi,

My questions is regarding tx_chain.v.

I am a bit confused as to how the flow of the code would proceed. There is
no "always" statement in the code.

First, two instances of cic_interp are instantiated .i.e.  cic_interp_i &
cic_interp_q . The signal assignments happen. The most significant signals
i_in and q_in are assigned to signal_in of cic_interp_i & cic_interp_q.

Question 1:

Do both (cic_interp_i & cic_interp_q) instantiation and assignment happen
at the execution time 0 ?

Or for that matter, all (cic_interp_i ,  cic_interp_q, phase_acc_tx &
tx_cordic_0) instantiations happen at time 0 ?

I am doubtful of what I am thinking above. Because I can see that
cic_interp_i's output signal bb_i is being assigned as input in tx_cordic_0.
So, if I go by my logic, then wrong assignments would happen.

Question 2:

Lets assume that some logic is defined for all (cic_interp_i ,
cic_interp_q, phase_acc_tx & tx_cordic_0) modules. And suppose cic_inter_i
module logic takes 5 clock cycles to finish its task and tx_cordic_0 module
logic takes 8 clock cycles to finish its task. So, will tx_cordic_0 wait for
5 clock cycles for cic_interp_i to finish its task, produce bb_i and then
tx_cordic_0 uses this new bb_i and then takes additional 8 clock cycles to
finish its task ?
So, total completion time would be 13 clock cycles ? Am I thinking right
or there is something wrong ?

Thanks !

Jetli.

P.S. Excuse me if my understanding sounds naive.

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Message: 4
Date: Fri, 30 Nov 2007 17:20:06 -0500
From: "Brian Padalino" <address@hidden>
Subject: Re: [Discuss-gnuradio] Re: tx_chain - Verilog question
To: "Ronald Jetli" <address@hidden>
Cc: address@hidden
Message-ID:
        <address@hidden>
Content-Type: text/plain; charset=ISO-8859-1

On Nov 30, 2007 5:01 PM, Ronald Jetli <address@hidden> wrote:
Hi,

I do understand that there are "always" statements in the base code and the
flow of those base code is clear to me.

It is just this top module, whose logic is not clear to me. I tried writing
a test bench, but that didnt help either.

It would be great if anyone could spare a minute and throw some light ?

This is just wiring a couple things together to get the transmission
chain to work at the full clock rate.  There are 3 main components
here: a phase accumulator, a CORDIC and an interpolating CIC filter.

The baseband signals are fed into the CORDIC along with a phase from
the phase accumulator.  For each sample that goes in, the phase
accumulator rotates.  This generates an IF that is mixed with your
baseband signal.

The interpolating CIC filter gets your baseband signal up to the
proper sample rate to feed the DACs.

To write a testbench, you would need to set the interpolation
frequency properly and if you wanted to use the CORDIC, that would
have to be setup properly as well for the phase accumulator.

You would then strobe your samples in at a rate of Fs where Fs is some
fraction of the total clock speed and Fs*interp_rate = the clock rate.
 You then have to strobe every Fs to send your samples through the
chain.

Hope this helps.

Brian




------------------------------

Message: 5
Date: Fri, 30 Nov 2007 18:29:56 -0500
From: "Ronald Jetli" <address@hidden>
Subject: Re: [Discuss-gnuradio] Re: tx_chain - Verilog question
To: "Brian Padalino" <address@hidden>
Cc: address@hidden
Message-ID:
        <address@hidden>
Content-Type: text/plain; charset="iso-8859-1"

Thank you Brian !

I am posting the test bench I am using to simulate / test tx_chain buffer.
I think it has
been set up properly to simulate CIC. And I do follow the steps while
stimulating.

However, I am having trouble setting up test cases for phase accumulator /
Cordic.

I am posting the code below. It should'nt take much change (atmost few
lines), but I am stuck with this one.It just dosent seem to work
for Cordic / Phase accumulator.

Can anyone please chip in ?

The Cordic test bench in fpga folder wasen't good either. It needs "sine.txt"
file, which is missing.

Thanks.

Jetli.

Testbench:
---------------


module tb;

  // Things that will be inputs to the device under test
  // (DUT) are declared as "reg" so I can write to them
  reg clock;
  reg reset;
  reg enable;
  reg sample_strobe;
  reg interpolator_strobe;
  reg [7:0] interp_rate ;
  reg [31:0] freq ;
  reg [15:0] i_in ;
  reg [15:0] q_in ;
  //int seed ;

  // Things that will be outputs from the DUT are wires.
  // Observe them with the simulator's waveform viewer.
  wire [15:0] i_out ;
  wire [15:0] q_out ;

  // The device under test
   tx_chain testing
(clock,reset,enable,interp_rate,sample_strobe,interpolator_strobe,freq,i_in,q_in,i_out,
q_out);



  reg stop;  // needed to stop simulation running for ever

  // Reset generator
  initial begin
    // Assert reset
    reset = 1'b1;
    // Wait for two clock cycles...
    repeat (2) @(negedge clock);
    // then deassert reset
    reset = 1'b0;
  end

  // clock generator
  initial begin
    stop = 1'b0;
    clock = 1'b0;
    while (!stop)
      #5 clock = ~clock;
  end

  // stimulus generator
  initial begin : stim_gen

   integer seed;

    // Set up seed for random stimulus generator
    seed = 42;

// Set up sensible values on control inputs

    interp_rate = 3;
    freq = 20;

    // Jamming input to true to see what happens.
    enable = 1'b1;

    // Now generating some input over the first 100 clocks
    repeat (100) @(negedge clock) begin
      // Randomly asserting strobe signals with 50% probability
      sample_strobe = $dist_uniform(seed, 0, 1);
      interpolator_strobe = $dist_uniform(seed, 0, 1);
      // Random 16-bit values on quadrature inputs
      i_in = $dist_uniform(seed, -32768, 32767);
      q_in = $dist_uniform(seed, -32768, 32767);
     // bb_i = $dist_uniform(seed, -32768, 32767);
    //  bb_q = $dist_uniform(seed, -32768, 32767);
    end

    // And finally stop:
    stop = 1;

  end

endmodule
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--
http://www.qsl.net/n1yvv
***********************************
****I'm not dead, yet!************
*********************************** Dave Ocame, WS1ETI Awards Chair
The SETILeague, Inc
www.setileague.org

Stony Creek Observatory FN31og -72.834 longitude 41.272 latitude Member: The SETILeague, Inc. and, The Society for Amateur Radio Astronomy (SARA) and,
The Planetary Society





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