Re: [Discuss-gnuradio] reading two rx channels on usrp2

[Eric Blossom]

On Tue, Jan 26, 2010 at 10:09:01PM -0500, Tom Gross wrote:
> I am in the process of hacking up the usrp2 host and firmware to
> support two receiver channels.  I'm at the point where
> "start_rx_streaming" is being acknowledged for channel 1 but there is
> no data being returned for that channel.  I don't actually understand
> yet where the receiver data is packaged to be sent over the ethernet
> (I haven't really looked into that yet) but I have been trying to
> understand how which receiver channel is selected...

The standard firmware and FPGA only implement a single channel.
There is only a single DDC instantiated in the FPGA.

> I'm guessing that the bits in rx_mux in dsp_rx_regs_t are used to
> connect one of two DACs to one (or two?) inputs of the digital down
> converter.  I note that the current setting of rx_mux is  0x44444444
> which I am guessing (based on the comments in memory_map.h) could mean
> "constant 0" for one input and "DAC A" for the other input to the
> DDC...  Am I interpreting that correctly?

No.

  /*!
   * \brief input mux configuration.
   *
   * This determines which ADC (or constant zero) is connected to 
   * each DDC input.  There are N DDCs (1 now).  Each has two inputs.
   *
   * <pre>
   * Mux value:
   *
   *    3                   2                   1                       
   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
   * +-------+-------+-------+-------+-------+-------+-------+-------+
   * |                                                       |Q0 |I0 |
   * +-------+-------+-------+-------+-------+-------+-------+-------+
   *
   * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
   * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
   *
   * The default value is 0x4
   * </pre>
   */
  volatile uint32_t     rx_mux;        // called adc_mux in dsp_core_rx.v

The bottom 4-bits of 0x44444444 connect A/D A to DDC0's I-input and
A/D B to DDC0's Q input.


> Can anyone give me some
> hints as to what the setting would be if I want to enable both
> channels?  Any other insights as to how to access both channels in the
> USRP2 firmware?

See comment above about there currently being only a single DDC in the
FPGA.  If you want two channels, amongst other things, you'll need to 
instantiate two DDCs, and add code that interleaves the samples from
the two DDCs.  You'll also have to create host and firmware that can
select the 1 or 2 channel case.

Eric