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Re: [Discuss-gnuradio] USRP synchronization

From: Eric Blossom
Subject: Re: [Discuss-gnuradio] USRP synchronization
Date: Tue, 9 Mar 2010 10:23:32 -0800
User-agent: Mutt/1.5.20 (2009-08-17)

On Tue, Mar 09, 2010 at 09:20:28AM -0800, ValentinG wrote:
> Hi All,
> We are trying to use 4 USRPs to extract the phase information due to
> differences in positions of the antennas.
> In a standard communications system an internally generated carrier is
> locked IN PHASE with the incoming signal to perform downconversion (see
> Figure 1.).
> http://old.nabble.com/file/p27838821/Fig%2B1%2BUSRP%2Bv2.jpg 
> As mentioned above we are using 4 USRPs to receive a signal from a single
> source. We wish to retain the phase information of this signal between boxes
> due to the different positions of the antennas. We feed all 4 boxes with a
> clock reference signal (10MHz, 1.5Vpk-pk), so that their internal clocks
> should be locked in phase with respect to each other. Are the internally
> generated carriers generated using this clock as a phase reference, i.e. is
> it correct, that this should also make all the internally generated carriers
> have zero phase difference between the boxes instead of locking to the
> phases of the incoming signals (see Figure 2.)?
> http://old.nabble.com/file/p27838821/Fig%2B2%2BUSRP%2Bv2.jpg 
> However, when we observe the internal clocks of 4 USRPs they are phase
> locked with respect to one another, but THERE IS A PHASE DIFFERENCE BETWEEN
> THEM, which is constant for a given power cycle. Does this imply that the
> phases of the internally generated carriers are locked to one another, but
> also with some NON 0 PHASE difference, i.e. that our actual system looks
> like Figure 3?
> http://old.nabble.com/file/p27838821/Fig%2B3%2BUSRP%2Bv3.jpg 
> Thanks,
> Valentin.

Matt can provide more info when he gets a chance, but I'm pretty sure
that what you're seeing is is normal and is due to the PLLs on the
daugherboards.  There's a finite number of phases that the PLL's will
lock to depending on the ratios programmed into the PLLs.  I don't
recall which daughterboards use integer-N vs fractional-N PLL's, but
they give different numbers of possible solutions.


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