On Wed, Sep 01, 2010 at 07:07:26PM -0600, Malihe Ahmadi wrote:
I am using USRP2+RFX2400 board and trying to adapt our packetized
communication on the board. As I understand the Ethernet does its
own packetization on information data and we don't like that.
therefore we are looking into avoid passing our information data to
the board through Ethernet. We are also fine to make the
configuration values for other peripherals on the board (such as
DAC, ADC and daughter boards) fixed so that we still can get away
with no Ethernet interface. so we are interested to know if there
is a general purpose input bus (at least 5 pins) that I can use to
pass my data serially to the FPGA.
The MICTOR debug connector, J301, has 32 uncommitted pins and 2 clks.
It's currently configured as an output, but you can use it for whatever
you like. Look in u2_rev3.v and/or u2_core.v.
output [31:0] debug,
output [1:0] debug_clk,
That means I would like to see if
it is possible to remove all the Verilog codes in FPGA related to
handling the Ethernet interface and get the data I'd like to process
through a general purpose input bus (at least 5 pins for clock and
serial data input and 3 handshaking signals) instead of Ethernet
port. For that reason, I need this general purpose bus to be
physically accessible on the board so that I can connect them to a
digital signal generator. Do you have any suggestion/recommendation