On Wed, Jun 29, 2011 at 10:30 AM, Ralf <address@hidden>
we are trying to use DPSK2 modulator and demodulator during our first trials.
As far as we can see there is hardly any documentation available on this.
We would appreciate a few explaining words from somebody who knows how to
configure the demodulator so that data is correctly received.
What synchronization method(s) is/are included?
Raised-cosine-filter for matched filtering seems to be included?
We tried like this with no success:
Excess BW: 0.35
Excess BW: 0.35
FLL Alpha: 0.01
Phase Alpha: 0.1
Timing Max Dev: 1.5
Omega Relative Limit: 0.005
Sync Out: ON
Thanks in advance!
The DPSK2 blocks use a frequency locked loop (FLL), a polyphase timing recovery loop, and a Costas loop for phase and residual frequency locking. Unfortunately, there are no magic numbers to use for these, but the defaults have worked well for me in the past.
I'll point out that the FLL in particular still needs work. It can get into oscillations pretty easily, and if that happens, the rest of your receiver chain won't work at all.
You can also turn on logging with --log to benchmark_rx.py, which dumps most pieces of the receiver chain to a file. You can then analyze the various parts of the receive path to see where things start to go wrong.
An common problem with the digital modulation code is if the frequency offset of the USRPs is too large between the TX and RX. It can be outside of the locking range and so never converge. To start with, it's a good idea to transmit with one radio and look at the spectrum with your receiver radio. Figure out the frequency delta between the two and compensate for it. It doesn't have to be exact, but just enough to get you close.