Hi Ron and Marcus,
For frequency higher than 6 Ghz, a down converter can be used to over come this problem.
for the data rate and bandwidth, the PC i'm using has the following specifications:
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 20
On-line CPU(s) list: 0-19
Thread(s) per core: 2
Core(s) per socket: 10
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 63
Model name: Intel(R) Xeon(R) CPU E5-2660 v3 @ 2.60GHz
Stepping: 2
CPU MHz: 1553.804
CPU max MHz: 3300.0000
CPU min MHz: 1200.0000
BogoMIPS: 5197.32
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 256K
L3 cache: 25600K
NUMA node0 CPU(s): 0-19
I think it can handle this rate. Please correct me if i'm Wrong.
i have other questions:
- There are (synchronizers, equalizers, channel codes etc) blocks in the gr-dvbt project why I cant use them?
- when you mentioned channel coding do you mean that i need to create a new one? and Why would I need it?
- If i need BCH performance Why is difficult to achieve?
- if the data requirement is fine (CPU and etc), what is the best way to start building the receiver? How can I figure out the blocks That i need for this receiver?
Regards
Ihab