[Emacs-diffs] master 852947b: Sync with upstream verilog-mode revision 0d6420b

[Glenn Morris]

branch: master
commit 852947baf0d71751843da82ec4593ea154fda9af
Author: Wilson Snyder <address@hidden>
Commit: Glenn Morris <address@hidden>

    Sync with upstream verilog-mode revision 0d6420b
    
    * lisp/progmodes/verilog-mode.el (verilog-mode-version): Update.
    (vector-skip-list): Remove.
    (verilog-auto-inst-port, verilog-auto-inst-port-list)
    (verilog-auto-inst, verilog-auto-inst-param):
    Use arguments rather than vector-skip.
    (verilog-auto-inst-port): Fix AUTOINST interfaces to not show modport
    if signal attachment is itself a modport.  Reported by Matthew Lovell.
---
 lisp/ChangeLog                 |   12 ++++++++++++
 lisp/progmodes/verilog-mode.el |   37 +++++++++++++++++++------------------
 2 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/lisp/ChangeLog b/lisp/ChangeLog
index 925f51b..4e59654 100644
--- a/lisp/ChangeLog
+++ b/lisp/ChangeLog
@@ -1,3 +1,15 @@
+2015-02-21  Wilson Snyder  <address@hidden>
+
+       Sync with upstream verilog-mode revision 0d6420b.
+       * progmodes/verilog-mode.el (verilog-mode-version): Update.
+       (vector-skip-list): Remove.
+       (verilog-auto-inst-port, verilog-auto-inst-port-list)
+       (verilog-auto-inst, verilog-auto-inst-param):
+       Use arguments rather than vector-skip.
+       (verilog-auto-inst-port): Fix AUTOINST interfaces to not show
+       modport if signal attachment is itself a modport.  Reported by
+       Matthew Lovell.
+
 2015-02-21  Reto Zimmermann  <address@hidden>
 
        Sync with upstream vhdl mode v3.37.1.  Add VHDL'08 support.
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index 7b6f2d3..5720654 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -123,7 +123,7 @@
 ;;; Code:
 
 ;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "2014-11-12-aa4b777-vpo"
+(defconst verilog-mode-version "2015-02-20-0d6420b-vpo"
   "Version of this Verilog mode.")
 (defconst verilog-mode-release-emacs t
   "If non-nil, this version of Verilog mode was released with Emacs itself.")
@@ -8419,7 +8419,6 @@ Return an array of [outputs inouts inputs wire reg assign 
const]."
   (defvar sigs-temp)
   ;; These are known to be from other packages and may not be defined
   (defvar diff-command nil)
-  (defvar vector-skip-list)
   ;; There are known to be from newer versions of Emacs
   (defvar create-lockfiles))
 
@@ -10884,7 +10883,7 @@ See the example in `verilog-auto-inout-modport'."
 (defvar vl-bits  nil "See `verilog-auto-inst'.") ; Prevent compile warning
 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
 
-(defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star 
par-values)
+(defun verilog-auto-inst-port (port-st indent-pt moddecls tpl-list tpl-num 
for-star par-values)
   "Print out an instantiation connection for this PORT-ST.
 Insert to INDENT-PT, use template TPL-LIST.
 @ are instantiation numbers, replaced with TPL-NUM.
@@ -10901,9 +10900,10 @@ If PAR-VALUES replace final strings with these 
parameter values."
         (vl-mbits (if (verilog-sig-multidim port-st)
                        (verilog-sig-multidim-string port-st) ""))
         (vl-bits (if (or verilog-auto-inst-vector
-                         (not (assoc port vector-skip-list))
+                         (not (assoc port (verilog-decls-get-signals 
moddecls)))
                          (not (equal (verilog-sig-bits port-st)
-                                     (verilog-sig-bits (assoc port 
vector-skip-list)))))
+                                     (verilog-sig-bits
+                                      (assoc port (verilog-decls-get-signals 
moddecls))))))
                      (or (verilog-sig-bits port-st) "")
                    ""))
         (case-fold-search nil)
@@ -10932,7 +10932,12 @@ If PAR-VALUES replace final strings with these 
parameter values."
                        (concat "/*" vl-mbits vl-bits "*/")
                      (concat vl-bits))
          tpl-net (concat port
-                         (if vl-modport (concat "." vl-modport) "")
+                         (if (and vl-modport
+                                  ;; .modport cannot be added if attachment is
+                                  ;; already declared as modport, VCS croaks
+                                  (let ((sig (assoc port 
(verilog-decls-get-interfaces moddecls))))
+                                    (not (and sig (verilog-sig-modport sig)))))
+                             (concat "." vl-modport) "")
                          dflt-bits))
     ;; Find template
     (cond (tpl-ass         ; Template of exact port name
@@ -11002,12 +11007,12 @@ If PAR-VALUES replace final strings with these 
parameter values."
 ;;(x "address@hidden"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
 ;;(x ".out (address@hidden"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
 
-(defun verilog-auto-inst-port-list (sig-list indent-pt tpl-list tpl-num 
for-star par-values)
+(defun verilog-auto-inst-port-list (sig-list indent-pt moddecls tpl-list 
tpl-num for-star par-values)
   "For `verilog-auto-inst' print a list of ports using 
`verilog-auto-inst-port'."
   (when verilog-auto-inst-sort
     (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
   (mapc (lambda (port)
-         (verilog-auto-inst-port port indent-pt
+         (verilog-auto-inst-port port indent-pt moddecls
                                  tpl-list tpl-num for-star par-values))
        sig-list))
 
@@ -11366,8 +11371,6 @@ For more information see the \\[verilog-faq] and forums 
at URL
                                          (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
           (modi (verilog-modi-current))
           (moddecls (verilog-modi-get-decls modi))
-          (vector-skip-list (unless verilog-auto-inst-vector
-                              (verilog-decls-get-signals moddecls)))
           submod submodi submoddecls
           inst skip-pins tpl-list tpl-num did-first par-values)
 
@@ -11409,7 +11412,7 @@ For more information see the \\[verilog-faq] and forums 
at URL
            (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
             ;; Note these are searched for in verilog-read-sub-decls.
            (verilog-insert-indent "// Interfaced\n")
-           (verilog-auto-inst-port-list sig-list indent-pt
+           (verilog-auto-inst-port-list sig-list indent-pt moddecls
                                         tpl-list tpl-num for-star par-values)))
        (let ((sig-list (verilog-signals-not-in
                         (verilog-decls-get-interfaces submoddecls)
@@ -11419,7 +11422,7 @@ For more information see the \\[verilog-faq] and forums 
at URL
            (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
             ;; Note these are searched for in verilog-read-sub-decls.
            (verilog-insert-indent "// Interfaces\n")
-           (verilog-auto-inst-port-list sig-list indent-pt
+           (verilog-auto-inst-port-list sig-list indent-pt moddecls
                                         tpl-list tpl-num for-star par-values)))
        (let ((sig-list (verilog-signals-not-in
                         (verilog-decls-get-outputs submoddecls)
@@ -11428,7 +11431,7 @@ For more information see the \\[verilog-faq] and forums 
at URL
          (when sig-list
            (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
            (verilog-insert-indent "// Outputs\n")
-           (verilog-auto-inst-port-list sig-list indent-pt
+           (verilog-auto-inst-port-list sig-list indent-pt moddecls
                                         tpl-list tpl-num for-star par-values)))
        (let ((sig-list (verilog-signals-not-in
                         (verilog-decls-get-inouts submoddecls)
@@ -11437,7 +11440,7 @@ For more information see the \\[verilog-faq] and forums 
at URL
          (when sig-list
            (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
            (verilog-insert-indent "// Inouts\n")
-           (verilog-auto-inst-port-list sig-list indent-pt
+           (verilog-auto-inst-port-list sig-list indent-pt moddecls
                                         tpl-list tpl-num for-star par-values)))
        (let ((sig-list (verilog-signals-not-in
                         (verilog-decls-get-inputs submoddecls)
@@ -11446,7 +11449,7 @@ For more information see the \\[verilog-faq] and forums 
at URL
          (when sig-list
            (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
            (verilog-insert-indent "// Inputs\n")
-           (verilog-auto-inst-port-list sig-list indent-pt
+           (verilog-auto-inst-port-list sig-list indent-pt moddecls
                                         tpl-list tpl-num for-star par-values)))
        ;; Kill extra semi
        (save-excursion
@@ -11509,8 +11512,6 @@ Templates:
                                          (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
           (modi (verilog-modi-current))
           (moddecls (verilog-modi-get-decls modi))
-          (vector-skip-list (unless verilog-auto-inst-vector
-                              (verilog-decls-get-signals moddecls)))
           submod submodi submoddecls
           inst skip-pins tpl-list tpl-num did-first)
       ;; Find module name that is instantiated
@@ -11550,7 +11551,7 @@ Templates:
            (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
             ;; Note these are searched for in verilog-read-sub-decls.
            (verilog-insert-indent "// Parameters\n")
-           (verilog-auto-inst-port-list sig-list indent-pt
+           (verilog-auto-inst-port-list sig-list indent-pt moddecls
                                         tpl-list tpl-num nil nil)))
        ;; Kill extra semi
        (save-excursion