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Re: [Gnu-arch-users] Re: arch performance with large trees
|
From: |
Catalin Marinas |
|
Subject: |
Re: [Gnu-arch-users] Re: arch performance with large trees |
|
Date: |
Thu, 10 Feb 2005 14:18:40 +0000 |
|
User-agent: |
Gnus/5.1007 (Gnus v5.10.7) Emacs/21.3 (gnu/linux) |
Paul Mundt <address@hidden> wrote:
> On Thu, Feb 10, 2005 at 11:19:31AM +0000, Catalin Marinas wrote:
>> Sad, but you can't do anything about it. I noticed yesterday that you
>> can't even get the full patch from bkbits.net using the BKrev number
>> for some changesets.
>>
> Do you have an example of this, this is somewhat in contrast to Larry's
> argument that everything is available via bkweb with the exception of BK
> metadata. It would be good if this issue was raised instead of the
> mindless political posturing that seems to dominate these threads.
I was debugging a system crash in the latest tree and removed several
patches (BKCVS converted to GNU Arch) until I got to the faulty
one (ChangeSet,v RCS revision - 1.26418, BKrev -
41fe523ecAJ3I6z55zHXaAI1vsDZ8Q). This changeset is actually a bundled
patch containing several changes. See the bkweb information for this
patch at:
http://linux.bkbits.net:8080/linux-2.5/address@hidden
http://linux.bkbits.net:8080/linux-2.5/address@hidden
I also attached the BKCVS log and the actual patch (generated by my
conversion script) for comparison. I would have thought that my script
is broken but the diff is consistent with the log (and one could
actually search the whole BKCVS repository for the "(Logical change
1.26418)" string.
Maybe I missed something but it is my impression that you can't
guarantee that the BKrev hash value can be consistently used.
Catalin
patch-3675
Description: Binary data
diff -Nru orig/Documentation/kernel-parameters.txt
mod/Documentation/kernel-parameters.txt
--- orig/Documentation/kernel-parameters.txt
+++ mod/Documentation/kernel-parameters.txt
@@ -226,15 +226,19 @@
atascsi= [HW,SCSI] Atari SCSI
- atkbd.extra= [HW] Enable extra LEDs and keys on IBM RapidAccess,
EzKey
- and similar keyboards
+ atkbd.extra= [HW] Enable extra LEDs and keys on IBM RapidAccess,
+ EzKey and similar keyboards
atkbd.reset= [HW] Reset keyboard during initialization
atkbd.set= [HW] Select keyboard code set
Format: <int> (2 = AT (default) 3 = PS/2)
- atkbd.scroll= [HW] Enable scroll wheel on MS Office and similar
keyboards
+ atkbd.scroll= [HW] Enable scroll wheel on MS Office and similar
+ keyboards
+
+ atkbd.softraw= [HW] Choose between synthetic and real raw mode
+ Format: <bool> (0 = real, 1 = synthetic (default))
atkbd.softrepeat=
[HW] Use software keyboard repeat
diff -Nru orig/arch/arm/kernel/entry-armv.S mod/arch/arm/kernel/entry-armv.S
--- orig/arch/arm/kernel/entry-armv.S
+++ mod/arch/arm/kernel/entry-armv.S
@@ -26,28 +26,27 @@
/*
* Invalid mode handlers
*/
-__pabt_invalid: sub sp, sp, #S_FRAME_SIZE @ Allocate
frame size in one go
- stmia sp, {r0 - lr} @ Save XXX r0 - lr
- ldr r4, .LCabt
- mov r1, #BAD_PREFETCH
+ .macro inv_entry, sym, reason
+ sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
+ stmia sp, {r0 - lr} @ Save XXX r0 - lr
+ ldr r4, .LC\sym
+ mov r1, #\reason
+ .endm
+
+__pabt_invalid:
+ inv_entry abt, BAD_PREFETCH
b 1f
-__dabt_invalid: sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - lr} @ Save SVC r0 - lr [lr
*should* be intact]
- ldr r4, .LCabt
- mov r1, #BAD_DATA
+__dabt_invalid:
+ inv_entry abt, BAD_DATA
b 1f
-__irq_invalid: sub sp, sp, #S_FRAME_SIZE @ Allocate space on
stack for frame
- stmfd sp, {r0 - lr} @ Save r0 - lr
- ldr r4, .LCirq
- mov r1, #BAD_IRQ
+__irq_invalid:
+ inv_entry irq, BAD_IRQ
b 1f
-__und_invalid: sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - lr}
- ldr r4, .LCund
- mov r1, #BAD_UNDEFINSTR @ int reason
+__und_invalid:
+ inv_entry und, BAD_UNDEFINSTR
1: zero_fp
ldmia r4, {r5 - r7} @ Get XXX pc, cpsr,
old_r0
@@ -60,15 +59,20 @@
/*
* SVC mode handlers
*/
+ .macro svc_entry, sym
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ save r0 - r12
+ ldr r2, .LC\sym
+ add r0, sp, #S_FRAME_SIZE
+ ldmia r2, {r2 - r4} @ get pc, cpsr
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc,
cpsr, old_ro
+ .endm
+
.align 5
-__dabt_svc: sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ save r0 - r12
- ldr r2, .LCabt
- add r0, sp, #S_FRAME_SIZE
- ldmia r2, {r2 - r4} @ get pc, cpsr
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC,
pc, cpsr, old_ro
+__dabt_svc:
+ svc_entry abt
mrs r9, cpsr @ Enable interrupts if
they were
tst r3, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT @ previously
@@ -91,14 +95,8 @@
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.align 5
-__irq_svc: sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ save r0 - r12
- ldr r7, .LCirq
- add r5, sp, #S_FRAME_SIZE
- ldmia r7, {r7 - r9}
- add r4, sp, #S_SP
- mov r6, lr
- stmia r4, {r5, r6, r7, r8, r9} @ save sp_SVC, lr_SVC,
pc, cpsr, old_ro
+__irq_svc:
+ svc_entry irq
#ifdef CONFIG_PREEMPT
get_thread_info r8
ldr r9, [r8, #TI_PREEMPT] @ get preempt count
@@ -148,16 +146,10 @@
#endif
.align 5
-__und_svc: sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ save r0 - r12
- ldr r3, .LCund
- mov r4, lr
- ldmia r3, {r5 - r7}
- add r3, sp, #S_FRAME_SIZE
- add r2, sp, #S_SP
- stmia r2, {r3 - r7} @ save sp_SVC, lr_SVC,
pc, cpsr, old_ro
+__und_svc:
+ svc_entry und
- ldr r0, [r5, #-4] @ r0 = instruction
+ ldr r0, [r2, #-4] @ r0 = instruction
adrsvc al, r9, 1f @ r9 = normal FP return
bl call_fpe @ lr = undefined instr
return
@@ -170,14 +162,8 @@
ldmia sp, {r0 - pc}^ @ Restore SVC registers
.align 5
-__pabt_svc: sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ save r0 - r12
- ldr r2, .LCabt
- add r0, sp, #S_FRAME_SIZE
- ldmia r2, {r2 - r4} @ get pc, cpsr
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC,
pc, cpsr, old_ro
+__pabt_svc:
+ svc_entry abt
mrs r9, cpsr @ Enable interrupts if
they were
tst r3, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT @ previously
@@ -205,15 +191,20 @@
/*
* User mode handlers
*/
+ .macro usr_entry, sym
+ sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
+ stmia sp, {r0 - r12} @ save r0 - r12
+ ldr r7, .LC\sym
+ add r5, sp, #S_PC
+ ldmia r7, {r2 - r4} @ Get USR pc, cpsr
+ stmia r5, {r2 - r4} @ Save USR pc, cpsr, old_r0
+ stmdb r5, {sp, lr}^
+ .endm
+
.align 5
-__dabt_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size
in one go
- stmia sp, {r0 - r12} @ save r0 - r12
- ldr r7, .LCabt
- add r5, sp, #S_PC
- ldmia r7, {r2 - r4} @ Get USR pc, cpsr
- stmia r5, {r2 - r4} @ Save USR pc, cpsr,
old_r0
- stmdb r5, {sp, lr}^
- alignment_trap r7, r7, __temp_abt
+__dabt_usr:
+ usr_entry abt
+ alignment_trap r7, r0, __temp_abt
zero_fp
#ifdef MULTI_ABORT
ldr r4, .LCprocfns @ pass r2, r3 to
@@ -228,14 +219,9 @@
b do_DataAbort
.align 5
-__irq_usr: sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ save r0 - r12
- ldr r4, .LCirq
- add r8, sp, #S_PC
- ldmia r4, {r5 - r7} @ get saved PC, SPSR
- stmia r8, {r5 - r7} @ save pc, psr, old_r0
- stmdb r8, {sp, lr}^
- alignment_trap r4, r7, __temp_irq
+__irq_usr:
+ usr_entry irq
+ alignment_trap r7, r0, __temp_irq
zero_fp
#ifdef CONFIG_PREEMPT
get_thread_info r8
@@ -265,18 +251,13 @@
.ltorg
.align 5
-__und_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size
in one go
- stmia sp, {r0 - r12} @ Save r0 - r12
- ldr r4, .LCund
- add r8, sp, #S_PC
- ldmia r4, {r5 - r7}
- stmia r8, {r5 - r7} @ Save USR pc, cpsr,
old_r0
- stmdb r8, {sp, lr}^ @ Save user sp, lr
- alignment_trap r4, r7, __temp_und
+__und_usr:
+ usr_entry und
+ alignment_trap r7, r0, __temp_und
zero_fp
- tst r6, #PSR_T_BIT @ Thumb mode?
+ tst r3, #PSR_T_BIT @ Thumb mode?
bne fpundefinstr @ ignore FP
- sub r4, r5, #4
+ sub r4, r2, #4
1: ldrt r0, [r4] @ r0 = instruction
adrsvc al, r9, ret_from_exception @ r9 = normal FP return
adrsvc al, lr, fpundefinstr @ lr = undefined instr
return
@@ -375,14 +356,9 @@
b do_undefinstr
.align 5
-__pabt_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size
in one go
- stmia sp, {r0 - r12} @ Save r0 - r12
- ldr r4, .LCabt
- add r8, sp, #S_PC
- ldmia r4, {r5 - r7} @ Get USR pc, cpsr
- stmia r8, {r5 - r7} @ Save USR pc, cpsr,
old_r0
- stmdb r8, {sp, lr}^ @ Save sp_usr lr_usr
- alignment_trap r4, r7, __temp_abt
+__pabt_usr:
+ usr_entry abt
+ alignment_trap r7, r0, __temp_abt
zero_fp
enable_irq r0 @ Enable interrupts
mov r0, r5 @ address (pc)
diff -Nru orig/arch/x86_64/mm/numa.c mod/arch/x86_64/mm/numa.c
--- orig/arch/x86_64/mm/numa.c
+++ mod/arch/x86_64/mm/numa.c
@@ -28,7 +28,6 @@
int memnode_shift;
u8 memnodemap[NODEMAPSIZE];
-#define NUMA_NO_NODE 0xff
unsigned char cpu_to_node[NR_CPUS] = { [0 ... NR_CPUS-1] = NUMA_NO_NODE };
cpumask_t node_to_cpumask[MAX_NUMNODES];
diff -Nru orig/arch/x86_64/mm/pageattr.c mod/arch/x86_64/mm/pageattr.c
--- orig/arch/x86_64/mm/pageattr.c
+++ mod/arch/x86_64/mm/pageattr.c
@@ -65,7 +65,10 @@
asm volatile("clflush (%0)" :: "r" (address + i));
} else
asm volatile("wbinvd":::"memory");
- __flush_tlb_one(address);
+ if (address)
+ __flush_tlb_one(address);
+ else
+ __flush_tlb_all();
}
@@ -217,6 +220,8 @@
down_read(&init_mm.mmap_sem);
df = xchg(&df_list, NULL);
up_read(&init_mm.mmap_sem);
+ if (!df)
+ return;
flush_map((df && !df->next) ? df->address : 0);
for (; df; df = next_df) {
next_df = df->next;
diff -Nru orig/arch/x86_64/mm/srat.c mod/arch/x86_64/mm/srat.c
--- orig/arch/x86_64/mm/srat.c
+++ mod/arch/x86_64/mm/srat.c
@@ -177,10 +177,18 @@
if (!node_isset(i, nodes_parsed))
continue;
cutoff_node(i, start, end);
- if (nodes[i].start == nodes[i].end)
+ if (nodes[i].start == nodes[i].end) {
+ node_clear(i, nodes_parsed);
continue;
+ }
setup_node_bootmem(i, nodes[i].start, nodes[i].end);
}
+ for (i = 0; i < NR_CPUS; i++) {
+ if (cpu_to_node[i] == NUMA_NO_NODE)
+ continue;
+ if (!node_isset(cpu_to_node[i], nodes_parsed))
+ cpu_to_node[i] = NUMA_NO_NODE;
+ }
numa_init_array();
return 0;
}
diff -Nru orig/drivers/block/cfq-iosched.c mod/drivers/block/cfq-iosched.c
--- orig/drivers/block/cfq-iosched.c
+++ mod/drivers/block/cfq-iosched.c
@@ -1285,19 +1285,19 @@
static void cfq_completed_request(request_queue_t *q, struct request *rq)
{
struct cfq_rq *crq = RQ_DATA(rq);
+ struct cfq_queue *cfqq;
if (unlikely(!blk_fs_request(rq)))
return;
- if (crq->in_flight) {
- struct cfq_queue *cfqq = crq->cfq_queue;
+ cfqq = crq->cfq_queue;
+ if (crq->in_flight) {
WARN_ON(!cfqq->in_flight);
cfqq->in_flight--;
-
- cfq_account_completion(cfqq, crq);
}
+ cfq_account_completion(cfqq, crq);
}
static struct request *
diff -Nru orig/drivers/char/watchdog/i8xx_tco.c
mod/drivers/char/watchdog/i8xx_tco.c
--- orig/drivers/char/watchdog/i8xx_tco.c
+++ mod/drivers/char/watchdog/i8xx_tco.c
@@ -1,5 +1,5 @@
/*
- * i8xx_tco 0.06: TCO timer driver for i8xx chipsets
+ * i8xx_tco 0.07: TCO timer driver for i8xx chipsets
*
* (c) Copyright 2000 kernel concepts <address@hidden>, All Rights
Reserved.
* http://www.kernelconcepts.de
@@ -22,11 +22,22 @@
*
* The TCO timer is implemented in the following I/O controller hubs:
* (See the intel documentation on http://developer.intel.com.)
- * 82801AA & 82801AB chip : document number 290655-003, 290677-004,
- * 82801BA & 82801BAM chip : document number 290687-002, 298242-005,
- * 82801CA & 82801CAM chip : document number 290716-001, 290718-001,
- * 82801DB & 82801E chip : document number 290744-001, 273599-001,
- * 82801EB & 82801ER chip : document number 252516-001
+ * 82801AA (ICH) : document number 290655-003, 290677-014,
+ * 82801AB (ICHO) : document number 290655-003, 290677-014,
+ * 82801BA (ICH2) : document number 290687-002, 298242-027,
+ * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
+ * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
+ * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
+ * 82801DB (ICH4) : document number 290744-001, 290745-020,
+ * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
+ * 82801E (C-ICH) : document number 273599-001, 273645-002,
+ * 82801EB (ICH5) : document number 252516-001, 252517-003,
+ * 82801ER (ICH5R) : document number 252516-001, 252517-003,
+ * 82801FB (ICH6) : document number 301473-002, 301474-007,
+ * 82801FR (ICH6R) : document number 301473-002, 301474-007,
+ * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
+ * 82801FW (ICH6W) : document number 301473-001, 301474-007,
+ * 82801FRW (ICH6RW) : document number 301473-001, 301474-007
*
* 20000710 Nils Faerber
* Initial Version 0.01
@@ -49,6 +60,9 @@
* 20030921 Wim Van Sebroeck <address@hidden>
* 0.06 change i810_margin to heartbeat, use module_param,
* added notify system support, renamed module to i8xx_tco.
+ * 20050128 Wim Van Sebroeck <address@hidden>
+ * 0.07 Added support for the ICH4-M, ICH6, ICH6R, ICH6-M, ICH6W and ICH6RW
+ * chipsets. Also added support for the "undocumented" ICH7 chipset.
*/
/*
@@ -73,7 +87,7 @@
#include "i8xx_tco.h"
/* Module and version information */
-#define TCO_VERSION "0.06"
+#define TCO_VERSION "0.07"
#define TCO_MODULE_NAME "i8xx TCO timer"
#define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
#define PFX TCO_MODULE_NAME ": "
@@ -360,8 +374,14 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, PCI_ANY_ID,
PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, PCI_ANY_ID,
PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, PCI_ANY_ID,
PCI_ANY_ID, },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, PCI_ANY_ID,
PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, PCI_ANY_ID,
PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, PCI_ANY_ID,
PCI_ANY_ID, },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, PCI_ANY_ID,
PCI_ANY_ID, },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, PCI_ANY_ID,
PCI_ANY_ID, },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2, PCI_ANY_ID,
PCI_ANY_ID, },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, PCI_ANY_ID,
PCI_ANY_ID, },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, PCI_ANY_ID,
PCI_ANY_ID, },
{ 0, }, /* End of list */
};
MODULE_DEVICE_TABLE (pci, i8xx_tco_pci_tbl);
diff -Nru orig/drivers/scsi/libata-scsi.c mod/drivers/scsi/libata-scsi.c
--- orig/drivers/scsi/libata-scsi.c
+++ mod/drivers/scsi/libata-scsi.c
@@ -282,7 +282,8 @@
/* No immediate match */
if(err)
printk(KERN_DEBUG "ata%u: no sense translation for 0x%02x\n",
qc->ap->id, err);
-
+
+ i = 0;
/* Fall back to interpreting status bits */
while(stat_table[i][0] != 0xFF)
{
diff -Nru orig/drivers/serial/s3c2410.c mod/drivers/serial/s3c2410.c
--- orig/drivers/serial/s3c2410.c
+++ mod/drivers/serial/s3c2410.c
@@ -744,11 +744,12 @@
unsigned long flags;
unsigned int baud, quot;
unsigned int ulcon;
+ unsigned int umcon;
/*
* We don't support modem control lines.
*/
- termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
+ termios->c_cflag &= ~(HUPCL | CMSPAR);
termios->c_cflag |= CLOCAL;
/*
@@ -806,8 +807,10 @@
if (termios->c_cflag & CSTOPB)
ulcon |= S3C2410_LCON_STOPB;
+ umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
+
if (termios->c_cflag & PARENB) {
- if (!(termios->c_cflag & PARODD))
+ if (termios->c_cflag & PARODD)
ulcon |= S3C2410_LCON_PODD;
else
ulcon |= S3C2410_LCON_PEVEN;
@@ -821,6 +824,7 @@
wr_regl(port, S3C2410_ULCON, ulcon);
wr_regl(port, S3C2410_UBRDIV, quot);
+ wr_regl(port, S3C2410_UMCON, umcon);
dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
rd_regl(port, S3C2410_ULCON),
diff -Nru orig/include/asm-arm/arch-lh7a40x/memory.h
mod/include/asm-arm/arch-lh7a40x/memory.h
--- orig/include/asm-arm/arch-lh7a40x/memory.h
+++ mod/include/asm-arm/arch-lh7a40x/memory.h
@@ -31,6 +31,8 @@
#ifdef CONFIG_DISCONTIGMEM
+#define NODES_SHIFT 4 /* Up to 16 nodes */
+
/*
* Given a kernel address, find the home node of the underlying memory.
*/
diff -Nru orig/include/asm-arm/arch-s3c2410/io.h
mod/include/asm-arm/arch-s3c2410/io.h
--- orig/include/asm-arm/arch-s3c2410/io.h
+++ mod/include/asm-arm/arch-s3c2410/io.h
@@ -65,12 +65,9 @@
return (unsigned sz)value; \
}
-static inline unsigned int __ioaddr (unsigned int port)
+static inline void __iomem *__ioaddr (unsigned int port)
{
- if (__PORT_PCIO(port))
- return (unsigned int)(PCIO_BASE + (port));
- else
- return (unsigned int)(0 + (port));
+ return (void __iomem *)(__PORT_PCIO(port) ? PCIO_BASE + port : port);
}
#define DECLARE_IO(sz,fnsuffix,instr) \
@@ -170,7 +167,7 @@
result; \
})
-#define __ioaddrc(port) (__PORT_PCIO((port)) ? PCIO_BASE + ((port)) :
((port)))
+#define __ioaddrc(port) ((void __iomem *)(__PORT_PCIO(port) ? PCIO_BASE
+ (port) : (port)))
#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
diff -Nru orig/include/asm-arm/arch-s3c2410/regs-serial.h
mod/include/asm-arm/arch-s3c2410/regs-serial.h
--- orig/include/asm-arm/arch-s3c2410/regs-serial.h
+++ mod/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -113,6 +113,9 @@
S3C2410_UFCON_TXTRIG0 | \
S3C2410_UFCON_RXTRIG8 )
+#define S3C2410_UMCOM_AFC (1<<4)
+#define S3C2410_UMCOM_RTS_LOW (1<<0)
+
#define S3C2410_UFSTAT_TXFULL (1<<9)
#define S3C2410_UFSTAT_RXFULL (1<<8)
#define S3C2410_UFSTAT_TXMASK (15<<4)
diff -Nru orig/include/asm-arm/numnodes.h mod/include/asm-arm/numnodes.h
--- orig/include/asm-arm/numnodes.h
+++ mod/include/asm-arm/numnodes.h
@@ -7,12 +7,17 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+
+/* This declaration for the size of the NUMA (CONFIG_DISCONTIGMEM)
+ * memory node table is the default.
+ *
+ * A good place to override this value is include/asm/arch/memory.h.
+ */
+
#ifndef __ASM_ARM_NUMNODES_H
#define __ASM_ARM_NUMNODES_H
-#ifdef CONFIG_ARCH_LH7A40X
-# define NODES_SHIFT 4 /* Max 16 nodes for the Sharp CPUs */
-#else
+#ifndef NODES_SHIFT
# define NODES_SHIFT 2 /* Normally, Max 4 Nodes */
#endif
diff -Nru orig/include/asm-x86_64/numa.h mod/include/asm-x86_64/numa.h
--- orig/include/asm-x86_64/numa.h
+++ mod/include/asm-x86_64/numa.h
@@ -16,4 +16,6 @@
extern void numa_init_array(void);
extern int numa_off;
+#define NUMA_NO_NODE 0xff
+
#endif
- Re: [Gnu-arch-users] Re: arch performance with large trees, (continued)
- Re: [Gnu-arch-users] Re: arch performance with large trees, Catalin Marinas, 2005/02/05
- [Gnu-arch-users] Re: arch performance with large trees, Miles Bader, 2005/02/07
- [Gnu-arch-users] Re: arch performance with large trees, Catalin Marinas, 2005/02/07
- [Gnu-arch-users] Re: arch performance with large trees, Miles Bader, 2005/02/07
- [Gnu-arch-users] Re: arch performance with large trees, Catalin Marinas, 2005/02/07
- [Gnu-arch-users] Re: arch performance with large trees, Miles Bader, 2005/02/07
- [Gnu-arch-users] Re: arch performance with large trees, Catalin Marinas, 2005/02/07
- [Gnu-arch-users] Re: arch performance with large trees, Miles Bader, 2005/02/10
- [Gnu-arch-users] Re: arch performance with large trees, Catalin Marinas, 2005/02/10
- Re: [Gnu-arch-users] Re: arch performance with large trees, Paul Mundt, 2005/02/10
- Re: [Gnu-arch-users] Re: arch performance with large trees,
Catalin Marinas <=
- Re: [Gnu-arch-users] Re: arch performance with large trees, mlh, 2005/02/10