Re: [Gnucap-devel] language plugin help

[address@hidden]

On Sun, Apr 15, 2012 at 9:24 PM, al davis <address@hidden> wrote:

> On Sunday 15 April 2012, John Griessen wrote:
> >  since when I've tried using verilog-a gnetlist output
> > with gnucap in the past, I only got partial functioning.
>
> That's true.
>
> To Felix and others .... John is referring to the "verilog"
> target of gnetlist, a part of gEDA, which is not part of Gnucap.
>
> The verilog target of gnetlist does not pass attributes, which
> are essential to the use of it with gnucap.  Also, the pin names
> are wrong in the sense that they do not follow established
> naming conventions.
>
> Gnucap's verilog input is "partial" too in the sense that it
> requires a netlist item to be on one line.
>
>
> I can post an example ...
>
> A resistor that should be outputed as:
>
> resistor #(.r( 3.)) R1 (.p(1),.n(2));
>
> is actually outputed as:
>
> RESISTOR R1 (
>    .\2  ( unnamed_net1 ),
>    .\1  ( unnamed_net6 )
>    );
>
> The defects:
> 1. No value for the resistor.
>

That's because there is no value for it in the attributes (i.e, in the
schematic file).
Infact when gnucap (gschem_lang) plugin will read schematic file, it can
generate a complete netlist which can be analyzed only if all attributes
were already there in the schematic to start with.

So, In case of missing attributes, Do we ask for user input for those... or
take some other default attribute value and prompt the user about it?

2. Pin names are "\2" and "\1".  They should be "p" and "n".


> The problem is partly with the symbol.  That is where the pin
> names are specified, and that is where the attributes come from.
>
> The pin name problem and attribute naming issue are common to
> both John's and Savant's work.
>
> The single line issue is a gnucap problem.
>
I assume modules cannot be used to define netlist in gnucap-verilog.

>
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-- 
Savant Krishna | Sophomore | Electrical Engineering | IIT Bombay