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[patch 2/3] PCI support (implementation from etherboot)


From: vincent guffens
Subject: [patch 2/3] PCI support (implementation from etherboot)
Date: Tue, 16 May 2006 22:38:27 +0100
User-agent: Mozilla Thunderbird 1.0.8 (X11/20060502)

Some directories, other than drivers/include/etherboot/i386 might have
to be created by hand.

2006-05-16  Vincent Guffens  <address@hidden>

        * drivers/include/etherboot/: New directory.
        * drivers/pci/i386/: Likewise.

        * configure.ac (AC_CONFIG_LINKS): Added drivers/include/etherboot/cpu
        links.

        * conf/i386-pc.rmk (pkgdata_MODULES): Added pci_etherboot.mod
        to the list of modules.
        (pci_etherboot_mod_SOURCES): Added.
        (pci_etherboot_mod_CFLAGS): Likewise.
        (pci_etherboot_mod_LDFLAGS): Likewise.

        * drivers/include/etherboot/pci_ids.h: New file.
        * drivers/include/etherboot/pci_defs.h: Likewise.
        * drivers/include/etherboot/i386/io.h: Likewise.
        * drivers/include/etherboot/i386/limits.h: Likewise.
        * drivers/pci/pci_etherboot.c: Likewise.
        * drivers/pci/i386/pci_io.c: Likewise.



diff -rNu grub2-pci/ChangeLog grub2-pci_etherboot/ChangeLog
--- grub2-pci/ChangeLog 2006-05-16 21:51:22.000000000 +0100
+++ grub2-pci_etherboot/ChangeLog       2006-05-16 21:51:44.000000000 +0100
@@ -1,5 +1,26 @@
 2006-05-16  Vincent Guffens  <address@hidden>

+       * drivers/include/etherboot/: New directory.
+       * drivers/pci/i386/: Likewise.
+
+       * configure.ac (AC_CONFIG_LINKS): Added drivers/include/etherboot/cpu
+       links.
+
+       * conf/i386-pc.rmk (pkgdata_MODULES): Added pci_etherboot.mod
+       to the list of modules.
+       (pci_etherboot_mod_SOURCES): Added.
+       (pci_etherboot_mod_CFLAGS): Likewise.
+       (pci_etherboot_mod_LDFLAGS): Likewise.
+
+       * drivers/include/etherboot/pci_ids.h: New file.
+       * drivers/include/etherboot/pci_defs.h: Likewise.
+       * drivers/include/etherboot/i386/io.h: Likewise.
+       * drivers/include/etherboot/i386/limits.h: Likewise.
+       * drivers/pci/pci_etherboot.c: Likewise.
+       * drivers/pci/i386/pci_io.c: Likewise.
+
+2006-05-16  Vincent Guffens  <address@hidden>
+
        * drivers/: New directory.

        * conf/i386-pc.rmk (pkgdata_MODULES): Added pci.mod
Binary files grub2-pci/.ChangeLog.swp and
grub2-pci_etherboot/.ChangeLog.swp differ
diff -rNu grub2-pci/conf/i386-pc.rmk grub2-pci_etherboot/conf/i386-pc.rmk
--- grub2-pci/conf/i386-pc.rmk  2006-05-16 21:07:30.000000000 +0100
+++ grub2-pci_etherboot/conf/i386-pc.rmk        2006-05-16 21:27:03.000000000 
+0100
@@ -117,7 +117,7 @@
 pkgdata_MODULES = _chain.mod _linux.mod linux.mod normal.mod \
        _multiboot.mod chain.mod multiboot.mod reboot.mod halt.mod      \
        vbe.mod vbetest.mod vbeinfo.mod video.mod gfxterm.mod \
-       videotest.mod play.mod pci.mod
+       videotest.mod play.mod pci.mod pci_etherboot.mod

 # For _chain.mod.
 _chain_mod_SOURCES = loader/i386/pc/chainloader.c
@@ -215,4 +215,9 @@
 pci_mod_CFLAGS = $(COMMON_CFLAGS) $(DRIVERS_CFLAGS)
 pci_mod_LDFLAGS = $(COMMON_LDFLAGS)

+# For pci_etherboot.mod
+pci_etherboot_mod_SOURCES = drivers/pci/pci_etherboot.c
drivers/pci/i386/pci_io.c
+pci_etherboot_mod_CFLAGS = $(COMMON_CFLAGS) $(DRIVERS_CFLAGS)
+pci_etherboot_mod_LDFLAGS = $(COMMON_LDFLAGS)
+
 include $(srcdir)/conf/common.mk
diff -rNu grub2-pci/configure.ac grub2-pci_etherboot/configure.ac
--- grub2-pci/configure.ac      2006-05-16 21:53:10.000000000 +0100
+++ grub2-pci_etherboot/configure.ac    2006-05-16 21:53:29.000000000 +0100
@@ -208,6 +208,7 @@

 # Output files.
 AC_CONFIG_LINKS([include/grub/cpu:include/grub/$host_cpu
+        drivers/include/etherboot/cpu:drivers/include/etherboot/$host_cpu
        include/grub/machine:include/grub/$host_cpu/$platform])
 AC_CONFIG_FILES([Makefile gensymlist.sh genkernsyms.sh])
 AC_CONFIG_FILES([stamp-h], [echo timestamp > stamp-h])
diff -rNu grub2-pci/drivers/include/etherboot/i386/io.h
grub2-pci_etherboot/drivers/include/etherboot/i386/io.h
--- grub2-pci/drivers/include/etherboot/i386/io.h       1970-01-01
01:00:00.000000000 +0100
+++ grub2-pci_etherboot/drivers/include/etherboot/i386/io.h     2006-05-16
21:31:31.000000000 +0100
@@ -0,0 +1,206 @@
+/* io.h - Architecture specific input/output functions  */
+/* Imported from Etherboot 5.4.1 */
+
+#ifndef        ETHERBOOT_IO_H
+#define ETHERBOOT_IO_H
+
+/*
+ * This file contains the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl and the "string versions" of the same
+ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
+ * versions of the single-IO instructions (inb_p/inw_p/..).
+ *
+ * This file is not meant to be obfuscating: it's just complicated
+ * to (a) handle it all in a way that makes gcc able to optimize it
+ * as well as possible and (b) trying to avoid writing the same thing
+ * over and over again with slight variations and possibly making a
+ * mistake somewhere.
+ */
+
+/*
+ * Thanks to James van Artsdalen for a better timing-fix than
+ * the two short jumps: using outb's to a nonexistent port seems
+ * to guarantee better timings even on fast machines.
+ *
+ * On the other hand, I'd like to be sure of a non-existent port:
+ * I feel a bit unsafe about using 0x80 (should be safe, though)
+ *
+ *             Linus
+ */
+
+#ifdef SLOW_IO_BY_JUMPING
+#define __SLOW_DOWN_IO __asm__ __volatile__("jmp 1f\n1:\tjmp 1f\n1:")
+#else
+#define __SLOW_DOWN_IO __asm__ __volatile__("outb %al,$0x80")
+#endif
+
+#ifdef REALLY_SLOW_IO
+#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO;
__SLOW_DOWN_IO; }
+#else
+#define SLOW_DOWN_IO __SLOW_DOWN_IO
+#endif
+
+/*
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the x86 architecture, we just read/write the
+ * memory location directly.
+ */
+#define readb(addr) (*(volatile unsigned char *) (addr))
+#define readw(addr) (*(volatile unsigned short *) (addr))
+#define readl(addr) (*(volatile unsigned int *) (addr))
+
+#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
+
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
+
+/*
+ * Force strict CPU ordering.
+ * And yes, this is required on UP too when we're talking
+ * to devices.
+ *
+ * For now, "wmb()" doesn't actually do anything, as all
+ * Intel CPU's follow what Intel calls a *Processor Order*,
+ * in which all writes are seen in the program order even
+ * outside the CPU.
+ *
+ * I expect future Intel CPU's to have a weaker ordering,
+ * but I'd also expect them to finally get their act together
+ * and add some real memory barriers if so.
+ *
+ * Some non intel clones support out of order store. wmb() ceases to be a
+ * nop for these.
+ */
+
+#define mb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
+#define rmb()  mb()
+#define wmb()  mb();
+
+
+/*
+ * Talk about misusing macros..
+ */
+
+#define __OUT1(s,x) \
+extern void __out##s(unsigned x value, unsigned short port); \
+extern inline void __out##s(unsigned x value, unsigned short port) {
+
+#define __OUT2(s,s1,s2) \
+__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
+
+#define __OUT(s,s1,x) \
+__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "d" (port)); } \
+__OUT1(s##c,x) __OUT2(s,s1,"") : : "a" (value), "id" (port)); } \
+__OUT1(s##_p,x) __OUT2(s,s1,"w") : : "a" (value), "d" (port));
SLOW_DOWN_IO; } \
+__OUT1(s##c_p,x) __OUT2(s,s1,"") : : "a" (value), "id" (port));
SLOW_DOWN_IO; }
+
+#define __IN1(s,x) \
+extern unsigned x __in##s(unsigned short port); \
+extern inline unsigned x __in##s(unsigned short port) { unsigned x _v;
+
+#define __IN2(s,s1,s2) \
+__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
+
+#define __IN(s,s1,x,i...) \
+__IN1(s,x) __IN2(s,s1,"w") : "=a" (_v) : "d" (port) ,##i ); return _v; } \
+__IN1(s##c,x) __IN2(s,s1,"") : "=a" (_v) : "id" (port) ,##i ); return
_v; } \
+__IN1(s##_p,x) __IN2(s,s1,"w") : "=a" (_v) : "d" (port) ,##i );
SLOW_DOWN_IO; return _v; } \
+__IN1(s##c_p,x) __IN2(s,s1,"") : "=a" (_v) : "id" (port) ,##i );
SLOW_DOWN_IO; return _v; }
+
+#define __INS(s) \
+extern void ins##s(unsigned short port, void * addr, unsigned long
count); \
+extern inline void ins##s(unsigned short port, void * addr, unsigned
long count) \
+{ __asm__ __volatile__ ("cld ; rep ; ins" #s \
+: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
+
+#define __OUTS(s) \
+extern void outs##s(unsigned short port, const void * addr, unsigned
long  count); \
+extern inline void outs##s(unsigned short port, const void * addr,
unsigned long count) \
+{ __asm__ __volatile__ ("cld ; rep ; outs" #s \
+: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
+
+__IN(b,"", char)
+__IN(w,"",short)
+__IN(l,"", long)
+
+__OUT(b,"b",char)
+__OUT(w,"w",short)
+__OUT(l,,int)
+
+__INS(b)
+__INS(w)
+__INS(l)
+
+__OUTS(b)
+__OUTS(w)
+__OUTS(l)
+
+/*
+ * Note that due to the way __builtin_constant_p() works, you
+ *  - can't use it inside a inline function (it will never be true)
+ *  - you don't have to worry about side effects within the __builtin..
+ */
+#define outb(val,port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __outbc((val),(port)) : \
+       __outb((val),(port)))
+
+#define inb(port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __inbc(port) : \
+       __inb(port))
+
+#define outb_p(val,port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __outbc_p((val),(port)) : \
+       __outb_p((val),(port)))
+
+#define inb_p(port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __inbc_p(port) : \
+       __inb_p(port))
+
+#define outw(val,port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __outwc((val),(port)) : \
+       __outw((val),(port)))
+
+#define inw(port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __inwc(port) : \
+       __inw(port))
+
+#define outw_p(val,port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __outwc_p((val),(port)) : \
+       __outw_p((val),(port)))
+
+#define inw_p(port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __inwc_p(port) : \
+       __inw_p(port))
+
+#define outl(val,port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __outlc((val),(port)) : \
+       __outl((val),(port)))
+
+#define inl(port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __inlc(port) : \
+       __inl(port))
+
+#define outl_p(val,port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __outlc_p((val),(port)) : \
+       __outl_p((val),(port)))
+
+#define inl_p(port) \
+((__builtin_constant_p((port)) && (port) < 256) ? \
+       __inlc_p(port) : \
+       __inl_p(port))
+
+#endif /* ETHERBOOT_IO_H */
diff -rNu grub2-pci/drivers/include/etherboot/i386/limits.h
grub2-pci_etherboot/drivers/include/etherboot/i386/limits.h
--- grub2-pci/drivers/include/etherboot/i386/limits.h   1970-01-01
01:00:00.000000000 +0100
+++ grub2-pci_etherboot/drivers/include/etherboot/i386/limits.h
2006-05-16 21:31:31.000000000 +0100
@@ -0,0 +1,8 @@
+#ifndef LIMITS_H
+#define LIMITS_H
+
+/* Maximum value an `unsigned long' can hold. (Minimum is 0.) */
+#define ULONG_MAX      4294967295UL
+
+#endif
+
diff -rNu grub2-pci/drivers/include/etherboot/pci_defs.h
grub2-pci_etherboot/drivers/include/etherboot/pci_defs.h
--- grub2-pci/drivers/include/etherboot/pci_defs.h      1970-01-01
01:00:00.000000000 +0100
+++ grub2-pci_etherboot/drivers/include/etherboot/pci_defs.h    2006-05-16
21:31:14.000000000 +0100
@@ -0,0 +1,229 @@
+/* This is verbatim from Etherboot (5.4.1) pci.h  */
+
+#include "pci_ids.h"
+
+#define PCI_COMMAND_IO                 0x1     /* Enable response in I/O space 
*/
+#define PCI_COMMAND_MEM                        0x2     /* Enable response in 
mem space */
+#define PCI_COMMAND_MASTER             0x4     /* Enable bus mastering */
+#define PCI_LATENCY_TIMER              0x0d    /* 8 bits */
+#define PCI_COMMAND_SPECIAL            0x8     /* Enable response to special 
cycles */
+#define PCI_COMMAND_INVALIDATE         0x10    /* Use memory write and 
invalidate */
+#define  PCI_COMMAND_VGA_PALETTE 0x20  /* Enable palette snooping */
+#define  PCI_COMMAND_PARITY    0x40    /* Enable parity checking */
+#define  PCI_COMMAND_WAIT      0x80    /* Enable address/data stepping */
+#define  PCI_COMMAND_SERR      0x100   /* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK 0x200   /* Enable back-to-back writes */
+
+#define PCIBIOS_PCI_FUNCTION_ID         0xb1XX
+#define PCIBIOS_PCI_BIOS_PRESENT        0xb101
+#define PCIBIOS_FIND_PCI_DEVICE         0xb102
+#define PCIBIOS_FIND_PCI_CLASS_CODE     0xb103
+#define PCIBIOS_GENERATE_SPECIAL_CYCLE  0xb106
+#define PCIBIOS_READ_CONFIG_BYTE        0xb108
+#define PCIBIOS_READ_CONFIG_WORD        0xb109
+#define PCIBIOS_READ_CONFIG_DWORD       0xb10a
+#define PCIBIOS_WRITE_CONFIG_BYTE       0xb10b
+#define PCIBIOS_WRITE_CONFIG_WORD       0xb10c
+#define PCIBIOS_WRITE_CONFIG_DWORD      0xb10d
+
+#define PCI_VENDOR_ID           0x00    /* 16 bits */
+#define PCI_DEVICE_ID           0x02    /* 16 bits */
+#define PCI_COMMAND             0x04    /* 16 bits */
+
+#define PCI_STATUS             0x06    /* 16 bits */
+#define  PCI_STATUS_CAP_LIST   0x10    /* Support Capability List */
+#define  PCI_STATUS_66MHZ      0x20    /* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF                0x40    /* Support User Definable 
Features
[obsolete] */
+#define  PCI_STATUS_FAST_BACK  0x80    /* Accept fast-back to back */
+#define  PCI_STATUS_PARITY     0x100   /* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK        0x600   /* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST        0x000   
+#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define  PCI_STATUS_DEVSEL_SLOW 0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+
+#define PCI_REVISION            0x08    /* 8 bits  */
+#define PCI_REVISION_ID         0x08    /* 8 bits  */
+#define PCI_CLASS_REVISION      0x08    /* 32 bits  */
+#define PCI_CLASS_CODE          0x0b    /* 8 bits */
+#define PCI_SUBCLASS_CODE       0x0a    /* 8 bits */
+#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL        0
+#define  PCI_HEADER_TYPE_BRIDGE 1
+#define  PCI_HEADER_TYPE_CARDBUS 2
+
+
+/* Header type 0 (normal devices) */
+#define PCI_CARDBUS_CIS                0x28
+#define PCI_SUBSYSTEM_VENDOR_ID        0x2c
+#define PCI_SUBSYSTEM_ID       0x2e
+
+#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
+#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
+#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
+#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
+#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
+#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
+
+#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
+#define PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
+#define PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
+
+#ifndef        PCI_BASE_ADDRESS_IO_MASK
+#define        PCI_BASE_ADDRESS_IO_MASK       (~0x03)
+#endif
+#ifndef        PCI_BASE_ADDRESS_MEM_MASK
+#define        PCI_BASE_ADDRESS_MEM_MASK       (~0x0f)
+#endif
+#define        PCI_BASE_ADDRESS_SPACE_IO       0x01
+#define        PCI_ROM_ADDRESS         0x30    /* 32 bits */
+#define        PCI_ROM_ADDRESS_ENABLE  0x01    /* Write 1 to enable ROM,
+                                          bits 31..11 are address,
+                                          10..2 are reserved */
+
+#define PCI_CAPABILITY_LIST    0x34    /* Offset of first capability list
entry */
+
+#define PCI_INTERRUPT_LINE     0x3c    /* IRQ number (0-15) */
+#define PCI_INTERRUPT_PIN      0x3d    /* IRQ pin on PCI bus (A-D) */
+
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS                0x18    /* Primary bus number */
+#define PCI_SECONDARY_BUS      0x19    /* Secondary bus number */
+#define PCI_SUBORDINATE_BUS    0x1a    /* Highest bus number behind the bridge 
*/
+#define PCI_SEC_LATENCY_TIMER  0x1b    /* Latency timer for secondary
interface */
+#define PCI_IO_BASE            0x1c    /* I/O range behind the bridge */
+#define PCI_IO_LIMIT           0x1d
+#define  PCI_IO_RANGE_TYPE_MASK        0x0f    /* I/O bridging type */
+#define  PCI_IO_RANGE_TYPE_16  0x00
+#define  PCI_IO_RANGE_TYPE_32  0x01
+#define  PCI_IO_RANGE_MASK     ~0x0f
+#define PCI_SEC_STATUS         0x1e    /* Secondary status register, only bit 
14
used */
+#define PCI_MEMORY_BASE                0x20    /* Memory range behind */
+#define PCI_MEMORY_LIMIT       0x22
+#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
+#define  PCI_MEMORY_RANGE_MASK ~0x0f
+#define PCI_PREF_MEMORY_BASE   0x24    /* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT  0x26
+#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
+#define  PCI_PREF_RANGE_TYPE_32        0x00
+#define  PCI_PREF_RANGE_TYPE_64        0x01
+#define  PCI_PREF_RANGE_MASK   ~0x0f
+#define PCI_PREF_BASE_UPPER32  0x28    /* Upper half of prefetchable memory
range */
+#define PCI_PREF_LIMIT_UPPER32 0x2c
+#define PCI_IO_BASE_UPPER16    0x30    /* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16   0x32
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
+#define PCI_ROM_ADDRESS1       0x38    /* Same as PCI_ROM_ADDRESS, but for 
htype
1 */
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_BRIDGE_CONTROL     0x3e
+#define  PCI_BRIDGE_CTL_PARITY 0x01    /* Enable parity detection on
secondary interface */
+#define  PCI_BRIDGE_CTL_SERR   0x02    /* The same for SERR forwarding */
+#define  PCI_BRIDGE_CTL_NO_ISA 0x04    /* Disable bridging of ISA ports */
+#define  PCI_BRIDGE_CTL_VGA    0x08    /* Forward VGA addresses */
+#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
+#define  PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
+#define  PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on
secondary interface */
+
+#define PCI_CB_CAPABILITY_LIST 0x14
+
+/* Capability lists */
+
+#define PCI_CAP_LIST_ID                0       /* Capability ID */
+#define  PCI_CAP_ID_PM         0x01    /* Power Management */
+#define  PCI_CAP_ID_AGP                0x02    /* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD                0x03    /* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID     0x04    /* Slot Identification */
+#define  PCI_CAP_ID_MSI                0x05    /* Message Signalled Interrupts 
*/
+#define  PCI_CAP_ID_CHSWP      0x06    /* CompactPCI HotSwap */
+#define PCI_CAP_LIST_NEXT      1       /* Next capability in the list */
+#define PCI_CAP_FLAGS          2       /* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF         4
+
+/* Power Management Registers */
+
+#define PCI_PM_PMC              2       /* PM Capabilities Register */
+#define  PCI_PM_CAP_VER_MASK   0x0007  /* Version */
+#define  PCI_PM_CAP_PME_CLOCK  0x0008  /* PME clock required */
+#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
+#define  PCI_PM_CAP_DSI                0x0020  /* Device specific 
initialization */
+#define  PCI_PM_CAP_AUX_POWER  0x01C0  /* Auxilliary power support mask */
+#define  PCI_PM_CAP_D1         0x0200  /* D1 power state support */
+#define  PCI_PM_CAP_D2         0x0400  /* D2 power state support */
+#define  PCI_PM_CAP_PME                0x0800  /* PME pin supported */
+#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported
states */
+#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
+#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
+#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
+#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
+#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
+#define PCI_PM_CTRL            4       /* PM control and status register */
+#define  PCI_PM_CTRL_STATE_MASK        0x0003  /* Current power state (D0 to 
D3) */
+#define  PCI_PM_CTRL_PME_ENABLE        0x0100  /* PME pin enable */
+#define  PCI_PM_CTRL_DATA_SEL_MASK     0x1e00  /* Data select (??) */
+#define  PCI_PM_CTRL_DATA_SCALE_MASK   0x6000  /* Data scale (??) */
+#define  PCI_PM_CTRL_PME_STATUS        0x8000  /* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS  6       /* PPB support extensions (??) */
+#define  PCI_PM_PPB_B2_B3      0x40    /* Stop clock when in D3hot (??) */
+#define  PCI_PM_BPCC_ENABLE    0x80    /* Bus power/clock control enable (??) 
*/
+#define PCI_PM_DATA_REGISTER   7       /* (??) */
+#define PCI_PM_SIZEOF          8
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION                2       /* BCD version number */
+#define PCI_AGP_RFU            3       /* Rest of capability flags */
+#define PCI_AGP_STATUS         4       /* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK        0xff000000      /* Maximum number of
requests - 1 */
+#define  PCI_AGP_STATUS_SBA    0x0200  /* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT  0x0020  /* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW     0x0010  /* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4  0x0004  /* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2  0x0002  /* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1  0x0001  /* 1x transfer rate supported */
+#define PCI_AGP_COMMAND                8       /* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number
of requests */
+#define  PCI_AGP_COMMAND_SBA   0x0200  /* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP   0x0100  /* Allow processing of AGP
transactions */
+#define  PCI_AGP_COMMAND_64BIT 0x0020  /* Allow processing of 64-bit
addresses */
+#define  PCI_AGP_COMMAND_FW    0x0010  /* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4 0x0004  /* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2 0x0002  /* Use 2x rate */
+#define  PCI_AGP_COMMAND_RATE1 0x0001  /* Use 1x rate */
+#define PCI_AGP_SIZEOF         12
+
+/* Slot Identification */
+
+#define PCI_SID_ESR            2       /* Expansion Slot Register */
+#define  PCI_SID_ESR_NSLOTS    0x1f    /* Number of expansion slots available 
*/
+#define  PCI_SID_ESR_FIC       0x20    /* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR     3       /* Chassis Number */
+
+/* Message Signalled Interrupts registers */
+
+#define PCI_MSI_FLAGS          2       /* Various flags */
+#define  PCI_MSI_FLAGS_64BIT   0x80    /* 64-bit addresses allowed */
+#define  PCI_MSI_FLAGS_QSIZE   0x70    /* Message queue size configured */
+#define  PCI_MSI_FLAGS_QMASK   0x0e    /* Maximum queue size available */
+#define  PCI_MSI_FLAGS_ENABLE  0x01    /* MSI feature enabled */
+#define PCI_MSI_RFU            3       /* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO     4       /* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI     8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT
set) */
+#define PCI_MSI_DATA_32                8       /* 16 bits of data for 32-bit 
devices */
+#define PCI_MSI_DATA_64                12      /* 16 bits of data for 64-bit 
devices */
+
+#define PCI_SLOT(devfn)                  ((devfn) >> 3)
+#define PCI_FUNC(devfn)           ((devfn) & 0x07)
+
+#define BIOS32_SIGNATURE        (('_' << 0) + ('3' << 8) + ('2' << 16)
+ ('_' << 24))
+
+/* PCI signature: "PCI " */
+#define PCI_SIGNATURE           (('P' << 0) + ('C' << 8) + ('I' << 16)
+ (' ' << 24))
+
+/* PCI service signature: "$PCI" */
+#define PCI_SERVICE             (('$' << 0) + ('P' << 8) + ('C' << 16)
+ ('I' << 24))
diff -rNu grub2-pci/drivers/include/etherboot/pci_ids.h
grub2-pci_etherboot/drivers/include/etherboot/pci_ids.h
--- grub2-pci/drivers/include/etherboot/pci_ids.h       1970-01-01
01:00:00.000000000 +0100
+++ grub2-pci_etherboot/drivers/include/etherboot/pci_ids.h     2006-05-16
21:31:14.000000000 +0100
@@ -0,0 +1,344 @@
+/* Verbatim from Etherboot 5.4.1 */
+/*
+ *     PCI Class, Vendor and Device IDs
+ *
+ *     Please keep sorted.
+ */
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED          0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA      0x0001
+
+#define PCI_BASE_CLASS_STORAGE         0x01
+#define PCI_CLASS_STORAGE_SCSI         0x0100
+#define PCI_CLASS_STORAGE_IDE          0x0101
+#define PCI_CLASS_STORAGE_FLOPPY       0x0102
+#define PCI_CLASS_STORAGE_IPI          0x0103
+#define PCI_CLASS_STORAGE_RAID         0x0104
+#define PCI_CLASS_STORAGE_OTHER                0x0180
+
+#define PCI_BASE_CLASS_NETWORK         0x02
+#define PCI_CLASS_NETWORK_ETHERNET     0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING   0x0201
+#define PCI_CLASS_NETWORK_FDDI         0x0202
+#define PCI_CLASS_NETWORK_ATM          0x0203
+#define PCI_CLASS_NETWORK_OTHER                0x0280
+
+#define PCI_BASE_CLASS_DISPLAY         0x03
+#define PCI_CLASS_DISPLAY_VGA          0x0300
+#define PCI_CLASS_DISPLAY_XGA          0x0301
+#define PCI_CLASS_DISPLAY_3D           0x0302
+#define PCI_CLASS_DISPLAY_OTHER                0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA      0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO     0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO     0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE     0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER     0x0480
+
+#define PCI_BASE_CLASS_MEMORY          0x05
+#define PCI_CLASS_MEMORY_RAM           0x0500
+#define PCI_CLASS_MEMORY_FLASH         0x0501
+#define PCI_CLASS_MEMORY_OTHER         0x0580
+
+#define PCI_BASE_CLASS_BRIDGE          0x06
+#define PCI_CLASS_BRIDGE_HOST          0x0600
+#define PCI_CLASS_BRIDGE_ISA           0x0601
+#define PCI_CLASS_BRIDGE_EISA          0x0602
+#define PCI_CLASS_BRIDGE_MC            0x0603
+#define PCI_CLASS_BRIDGE_PCI           0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA                0x0605
+#define PCI_CLASS_BRIDGE_NUBUS         0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS       0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY       0x0608
+#define PCI_CLASS_BRIDGE_OTHER         0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION   0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM  0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER  0x0780
+
+#define PCI_BASE_CLASS_SYSTEM          0x08
+#define PCI_CLASS_SYSTEM_PIC           0x0800
+#define PCI_CLASS_SYSTEM_DMA           0x0801
+#define PCI_CLASS_SYSTEM_TIMER         0x0802
+#define PCI_CLASS_SYSTEM_RTC           0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG   0x0804
+#define PCI_CLASS_SYSTEM_OTHER         0x0880
+
+#define PCI_BASE_CLASS_INPUT           0x09
+#define PCI_CLASS_INPUT_KEYBOARD       0x0900
+#define PCI_CLASS_INPUT_PEN            0x0901
+#define PCI_CLASS_INPUT_MOUSE          0x0902
+#define PCI_CLASS_INPUT_SCANNER                0x0903
+#define PCI_CLASS_INPUT_GAMEPORT       0x0904
+#define PCI_CLASS_INPUT_OTHER          0x0980
+
+#define PCI_BASE_CLASS_DOCKING         0x0a
+#define PCI_CLASS_DOCKING_GENERIC      0x0a00
+#define PCI_CLASS_DOCKING_OTHER                0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR       0x0b
+#define PCI_CLASS_PROCESSOR_386                0x0b00
+#define PCI_CLASS_PROCESSOR_486                0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM    0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA      0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC    0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS       0x0b30
+#define PCI_CLASS_PROCESSOR_CO         0x0b40
+
+#define PCI_BASE_CLASS_SERIAL          0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE      0x0c00
+#define PCI_CLASS_SERIAL_ACCESS                0x0c01
+#define PCI_CLASS_SERIAL_SSA           0x0c02
+#define PCI_CLASS_SERIAL_USB           0x0c03
+#define PCI_CLASS_SERIAL_FIBER         0x0c04
+#define PCI_CLASS_SERIAL_SMBUS         0x0c05
+
+#define PCI_BASE_CLASS_INTELLIGENT     0x0e
+#define PCI_CLASS_INTELLIGENT_I2O      0x0e00
+
+#define PCI_BASE_CLASS_SATELLITE       0x0f
+#define PCI_CLASS_SATELLITE_TV         0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO      0x0f01
+#define PCI_CLASS_SATELLITE_VOICE      0x0f03
+#define PCI_CLASS_SATELLITE_DATA       0x0f04
+
+#define PCI_BASE_CLASS_CRYPT           0x10
+#define PCI_CLASS_CRYPT_NETWORK                0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT  0x1001
+#define PCI_CLASS_CRYPT_OTHER          0x1080
+
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define PCI_CLASS_SP_DPIO              0x1100
+#define PCI_CLASS_SP_OTHER             0x1180
+
+#define PCI_CLASS_OTHERS               0xff
+
+/* Vendors */
+
+#define PCI_VENDOR_ID_DYNALINK         0x0675
+#define PCI_VENDOR_ID_BERKOM                   0x0871
+#define PCI_VENDOR_ID_COMPAQ           0x0e11
+#define PCI_VENDOR_ID_NCR              0x1000
+#define PCI_VENDOR_ID_LSI_LOGIC                0x1000
+#define PCI_VENDOR_ID_ATI              0x1002
+#define PCI_VENDOR_ID_VLSI             0x1004
+#define PCI_VENDOR_ID_ADL              0x1005
+#define PCI_VENDOR_ID_NS               0x100b
+#define PCI_VENDOR_ID_TSENG            0x100c
+#define PCI_VENDOR_ID_WEITEK           0x100e
+#define PCI_VENDOR_ID_DEC              0x1011
+#define PCI_VENDOR_ID_CIRRUS           0x1013
+#define PCI_VENDOR_ID_IBM              0x1014
+#define PCI_VENDOR_ID_COMPEX2          0x101a
+/* pci.ids says "AT&T GIS (NCR)" */
+#define PCI_VENDOR_ID_WD               0x101c
+#define PCI_VENDOR_ID_AMI              0x101e
+#define PCI_VENDOR_ID_AMD              0x1022
+#define PCI_VENDOR_ID_TRIDENT          0x1023
+#define PCI_VENDOR_ID_AI               0x1025
+#define PCI_VENDOR_ID_DELL              0x1028
+#define PCI_VENDOR_ID_MATROX           0x102B
+#define PCI_VENDOR_ID_CT               0x102c
+#define PCI_VENDOR_ID_MIRO             0x1031
+#define PCI_VENDOR_ID_NEC              0x1033
+#define PCI_VENDOR_ID_FD               0x1036
+#define PCI_VENDOR_ID_SIS              0x1039
+#define PCI_VENDOR_ID_SI               0x1039
+#define PCI_VENDOR_ID_HP               0x103c
+#define PCI_VENDOR_ID_PCTECH           0x1042
+#define PCI_VENDOR_ID_ASUSTEK          0x1043
+#define PCI_VENDOR_ID_DPT              0x1044
+#define PCI_VENDOR_ID_OPTI             0x1045
+#define PCI_VENDOR_ID_ELSA             0x1048
+#define PCI_VENDOR_ID_ELSA             0x1048
+#define PCI_VENDOR_ID_SGS              0x104a
+#define PCI_VENDOR_ID_BUSLOGIC               0x104B
+#define PCI_VENDOR_ID_TI               0x104c
+#define PCI_VENDOR_ID_SONY             0x104d
+#define PCI_VENDOR_ID_OAK              0x104e
+/* Winbond have two vendor IDs! See 0x10ad as well */
+#define PCI_VENDOR_ID_WINBOND2         0x1050
+#define PCI_VENDOR_ID_ANIGMA           0x1051
+#define PCI_VENDOR_ID_EFAR             0x1055
+#define PCI_VENDOR_ID_MOTOROLA         0x1057
+#define PCI_VENDOR_ID_MOTOROLA_OOPS    0x1507
+#define PCI_VENDOR_ID_PROMISE          0x105a
+#define PCI_VENDOR_ID_N9               0x105d
+#define PCI_VENDOR_ID_UMC              0x1060
+#define PCI_VENDOR_ID_X                        0x1061
+#define PCI_VENDOR_ID_MYLEX            0x1069
+#define PCI_VENDOR_ID_PICOP            0x1066
+#define PCI_VENDOR_ID_APPLE            0x106b
+#define PCI_VENDOR_ID_YAMAHA           0x1073
+#define PCI_VENDOR_ID_NEXGEN           0x1074
+#define PCI_VENDOR_ID_QLOGIC           0x1077
+#define PCI_VENDOR_ID_CYRIX            0x1078
+#define PCI_VENDOR_ID_LEADTEK          0x107d
+#define PCI_VENDOR_ID_INTERPHASE       0x107e
+#define PCI_VENDOR_ID_CONTAQ           0x1080
+#define PCI_VENDOR_ID_FOREX            0x1083
+#define PCI_VENDOR_ID_OLICOM           0x108d
+#define PCI_VENDOR_ID_SUN              0x108e
+#define PCI_VENDOR_ID_CMD              0x1095
+#define PCI_VENDOR_ID_VISION           0x1098
+#define PCI_VENDOR_ID_BROOKTREE                0x109e
+#define PCI_VENDOR_ID_SIERRA           0x10a8
+#define PCI_VENDOR_ID_SGI              0x10a9
+#define PCI_VENDOR_ID_ACC              0x10aa
+#define PCI_VENDOR_ID_WINBOND          0x10ad
+#define PCI_VENDOR_ID_DATABOOK         0x10b3
+#define PCI_VENDOR_ID_PLX              0x10b5
+#define PCI_VENDOR_ID_MADGE            0x10b6
+#define PCI_VENDOR_ID_3COM             0x10b7
+#define PCI_VENDOR_ID_SMC              0x10b8
+#define PCI_VENDOR_ID_SUNDANCE         0x13F0
+#define PCI_VENDOR_ID_AL               0x10b9
+#define PCI_VENDOR_ID_MITSUBISHI       0x10ba
+#define PCI_VENDOR_ID_SURECOM          0x10bd
+#define PCI_VENDOR_ID_NEOMAGIC         0x10c8
+#define PCI_VENDOR_ID_ASP              0x10cd
+#define PCI_VENDOR_ID_MACRONIX         0x10d9
+#define PCI_VENDOR_ID_TCONRAD          0x10da
+#define PCI_VENDOR_ID_CERN             0x10dc
+#define PCI_VENDOR_ID_NVIDIA                   0x10de
+#define PCI_VENDOR_ID_IMS              0x10e0
+#define PCI_VENDOR_ID_TEKRAM2          0x10e1
+#define PCI_VENDOR_ID_TUNDRA           0x10e3
+#define PCI_VENDOR_ID_AMCC             0x10e8
+#define PCI_VENDOR_ID_INTERG           0x10ea
+#define PCI_VENDOR_ID_REALTEK          0x10ec
+#define PCI_VENDOR_ID_XILINX           0x10ee
+#define PCI_VENDOR_ID_TRUEVISION       0x10fa
+#define PCI_VENDOR_ID_INIT             0x1101
+#define PCI_VENDOR_ID_CREATIVE         0x1102
+/* duplicate: ECTIVA */
+#define PCI_VENDOR_ID_ECTIVA           0x1102
+/* duplicate: CREATIVE */
+#define PCI_VENDOR_ID_TTI              0x1103
+#define PCI_VENDOR_ID_VIA              0x1106
+#define PCI_VENDOR_ID_VIATEC           0x1106
+#define PCI_VENDOR_ID_SIEMENS           0x110A
+#define PCI_VENDOR_ID_SMC2             0x1113
+#define PCI_VENDOR_ID_VORTEX           0x1119
+#define PCI_VENDOR_ID_EF               0x111a
+#define PCI_VENDOR_ID_IDT              0x111d
+#define PCI_VENDOR_ID_FORE             0x1127
+#define PCI_VENDOR_ID_IMAGINGTECH      0x112f
+#define PCI_VENDOR_ID_PHILIPS          0x1131
+#define PCI_VENDOR_ID_EICON            0x1133
+#define PCI_VENDOR_ID_CYCLONE          0x113c
+#define PCI_VENDOR_ID_ALLIANCE         0x1142
+#define PCI_VENDOR_ID_SYSKONNECT       0x1148
+#define PCI_VENDOR_ID_VMIC             0x114a
+#define PCI_VENDOR_ID_DIGI             0x114f
+#define PCI_VENDOR_ID_MUTECH           0x1159
+#define PCI_VENDOR_ID_XIRCOM           0x115d
+#define PCI_VENDOR_ID_RENDITION                0x1163
+#define PCI_VENDOR_ID_SERVERWORKS        0x1166
+#define PCI_VENDOR_ID_SBE              0x1176
+#define PCI_VENDOR_ID_TOSHIBA          0x1179
+#define PCI_VENDOR_ID_RICOH            0x1180
+#define        PCI_VENDOR_ID_DLINK             0x1186
+#define PCI_VENDOR_ID_ARTOP            0x1191
+#define PCI_VENDOR_ID_ZEITNET          0x1193
+#define PCI_VENDOR_ID_OMEGA            0x119b
+#define PCI_VENDOR_ID_FUJITSU_ME       0x119e
+#define PCI_SUBVENDOR_ID_KEYSPAN       0x11a9
+#define PCI_VENDOR_ID_GALILEO          0x11ab
+#define PCI_VENDOR_ID_LINKSYS          0x11ad
+#define PCI_VENDOR_ID_LITEON           0x11ad
+#define PCI_VENDOR_ID_V3               0x11b0
+#define PCI_VENDOR_ID_NP               0x11bc
+#define PCI_VENDOR_ID_ATT              0x11c1
+#define PCI_VENDOR_ID_SPECIALIX                0x11cb
+#define PCI_VENDOR_ID_AURAVISION       0x11d1
+#define PCI_VENDOR_ID_ANALOG_DEVICES   0x11d4
+#define PCI_VENDOR_ID_IKON             0x11d5
+#define PCI_VENDOR_ID_ZORAN            0x11de
+#define PCI_VENDOR_ID_KINETIC          0x11f4
+#define PCI_VENDOR_ID_COMPEX           0x11f6
+#define PCI_VENDOR_ID_RP               0x11fe
+#define PCI_VENDOR_ID_CYCLADES         0x120e
+#define PCI_VENDOR_ID_ESSENTIAL                0x120f
+#define PCI_VENDOR_ID_O2               0x1217
+#define PCI_VENDOR_ID_3DFX             0x121a
+#define PCI_VENDOR_ID_SIGMADES         0x1236
+#define PCI_VENDOR_ID_CCUBE            0x123f
+#define PCI_VENDOR_ID_AVM              0x1244
+#define PCI_VENDOR_ID_DIPIX            0x1246
+#define PCI_VENDOR_ID_STALLION         0x124d
+#define PCI_VENDOR_ID_OPTIBASE         0x1255
+#define PCI_VENDOR_ID_ESS              0x125d
+#define PCI_VENDOR_ID_HARRIS           0x1260
+#define PCI_VENDOR_ID_SATSAGEM         0x1267
+#define PCI_VENDOR_ID_HUGHES           0x1273
+#define PCI_VENDOR_ID_ENSONIQ          0x1274
+#define PCI_VENDOR_ID_ROCKWELL         0x127A
+#define PCI_VENDOR_ID_DAVICOM          0x1282
+#define PCI_VENDOR_ID_ITE              0x1283
+/* formerly Platform Tech */
+#define PCI_VENDOR_ID_ESS_OLD          0x1285
+#define PCI_VENDOR_ID_ALTEON           0x12ae
+#define PCI_VENDOR_ID_USR              0x12B9
+#define        PCI_VENDOR_ID_HOLTEK            0x12c3
+#define PCI_SUBVENDOR_ID_CONNECT_TECH                  0x12c4
+#define PCI_VENDOR_ID_PICTUREL         0x12c5
+#define PCI_VENDOR_ID_NVIDIA_SGS       0x12d2
+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST         0x12E0
+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS          0x124D
+#define PCI_VENDOR_ID_AUREAL           0x12eb
+#define PCI_VENDOR_ID_CBOARDS          0x1307
+#define PCI_VENDOR_ID_SIIG             0x131f
+#define PCI_VENDOR_ID_ADMTEK            0x1317
+#define PCI_VENDOR_ID_DOMEX            0x134a
+#define PCI_VENDOR_ID_QUATECH          0x135C
+#define PCI_VENDOR_ID_SEALEVEL         0x135e
+#define PCI_VENDOR_ID_HYPERCOPE                0x1365
+#define PCI_VENDOR_ID_KAWASAKI         0x136b
+#define PCI_VENDOR_ID_LMC              0x1376
+#define PCI_VENDOR_ID_NETGEAR          0x1385
+#define PCI_VENDOR_ID_APPLICOM         0x1389
+#define PCI_VENDOR_ID_MOXA             0x1393
+#define PCI_VENDOR_ID_CCD              0x1397
+#define PCI_VENDOR_ID_MICROGATE                0x13c0
+#define PCI_VENDOR_ID_3WARE            0x13C1
+#define PCI_VENDOR_ID_ABOCOM           0x13D1
+#define PCI_VENDOR_ID_CMEDIA           0x13f6
+#define PCI_VENDOR_ID_LAVA             0x1407
+#define PCI_VENDOR_ID_TIMEDIA          0x1409
+#define PCI_VENDOR_ID_OXSEMI           0x1415
+#define PCI_VENDOR_ID_AIRONET          0x14b9
+#define PCI_VENDOR_ID_TITAN            0x14D2
+#define PCI_VENDOR_ID_PANACOM          0x14d4
+#define PCI_VENDOR_ID_BROADCOM         0x14e4
+#define PCI_VENDOR_ID_SYBA             0x1592
+#define PCI_VENDOR_ID_MORETON          0x15aa
+#define PCI_VENDOR_ID_ZOLTRIX          0x15b0
+#define PCI_VENDOR_ID_PDC              0x15e9
+#define PCI_VENDOR_ID_FSC              0x1734
+#define PCI_VENDOR_ID_SYMPHONY         0x1c1c
+#define PCI_VENDOR_ID_TEKRAM           0x1de1
+#define PCI_VENDOR_ID_3DLABS           0x3d3d
+#define PCI_VENDOR_ID_AVANCE           0x4005
+#define PCI_VENDOR_ID_AKS              0x416c
+#define PCI_VENDOR_ID_NETVIN           0x4a14
+#define PCI_VENDOR_ID_S3               0x5333
+#define PCI_VENDOR_ID_DCI              0x6666
+#define PCI_VENDOR_ID_GENROCO          0x5555
+#define PCI_VENDOR_ID_INTEL            0x8086
+#define PCI_VENDOR_ID_COMPUTONE                0x8e0e
+#define PCI_SUBVENDOR_ID_COMPUTONE     0x8e0e
+#define PCI_VENDOR_ID_KTI              0x8e2e
+#define PCI_VENDOR_ID_ADAPTEC          0x9004
+#define PCI_VENDOR_ID_ADAPTEC2         0x9005
+#define PCI_VENDOR_ID_ATRONICS         0x907f
+#define PCI_VENDOR_ID_HOLTEK2          0x9412
+#define PCI_VENDOR_ID_NETMOS           0x9710
+#define PCI_SUBVENDOR_ID_EXSYS         0xd84d
+#define PCI_VENDOR_ID_TIGERJET         0xe159
+#define PCI_VENDOR_ID_ARK              0xedd8
diff -rNu grub2-pci/drivers/pci/i386/pci_io.c
grub2-pci_etherboot/drivers/pci/i386/pci_io.c
--- grub2-pci/drivers/pci/i386/pci_io.c 1970-01-01 01:00:00.000000000 +0100
+++ grub2-pci_etherboot/drivers/pci/i386/pci_io.c       2006-05-16
21:32:02.000000000 +0100
@@ -0,0 +1,80 @@
+/* pci_io.c : Architecture specific PCI IO functions,
+              Adapted from Etherboot 5.4.1 - pci_io.c    */
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <grub/pci.h>
+#include <etherboot/i386/io.h>
+
+
+#define CONFIG_CMD(dev, where)  \
+  (0x80000000 | (dev->bus << 16) |  (dev->devfn << 8) | (where & ~3))
+
+static grub_err_t read_config_byte (grub_pci_device_t dev, grub_addr_t
where,
+                             grub_uint8_t *value)
+{
+  outl(CONFIG_CMD(dev, where), 0xCF8);
+  *value = inb(0xCFC + (where&3));
+  return GRUB_ERR_NONE;
+}
+
+static grub_err_t write_config_byte (grub_pci_device_t dev, grub_addr_t
where,
+                              grub_uint8_t value)
+{
+  outl(CONFIG_CMD(dev, where), 0xCF8);
+  outb(value, 0xCFC + (where&3));
+  return GRUB_ERR_NONE;
+}
+
+static grub_err_t read_config_word (grub_pci_device_t dev, grub_addr_t
where,
+                             grub_uint16_t *value)
+{
+  outl(CONFIG_CMD(dev, where), 0xCF8);
+  *value = inw(0xCFC + (where&2));
+  return GRUB_ERR_NONE;
+}
+
+static grub_err_t write_config_word (grub_pci_device_t dev, grub_addr_t
where,
+                              grub_uint16_t value)
+{
+  outl(CONFIG_CMD(dev, where), 0xCF8);
+  outw(value, 0xCFC + (where&2));
+  return GRUB_ERR_NONE;
+}
+
+static grub_err_t read_config_dword (grub_pci_device_t dev, grub_addr_t
where,
+                              grub_uint32_t *value)
+{
+  outl(CONFIG_CMD(dev, where), 0xCF8);
+  *value = inl(0xCFC);
+  return GRUB_ERR_NONE;
+}
+
+static grub_err_t write_config_dword (grub_pci_device_t dev,
grub_addr_t where,
+                               grub_uint32_t value)
+{
+  outl(CONFIG_CMD(dev, where), 0xCF8);
+  outw(value, 0xCFC + (where&2));
+  return GRUB_ERR_NONE;
+}
+
+static grub_addr_t bus_base (unsigned int bus __attribute__((unused)))
+{
+       /* architecturally this must be 0 */
+       return 0;
+}
+
+struct grub_pci_io_support grub_pci_io_support_etherboot =
+  {
+    read_config_byte,
+    write_config_byte,
+    read_config_word,
+    write_config_word,
+    read_config_dword,
+    write_config_dword,
+    bus_base
+  };
diff -rNu grub2-pci/drivers/pci/pci_etherboot.c
grub2-pci_etherboot/drivers/pci/pci_etherboot.c
--- grub2-pci/drivers/pci/pci_etherboot.c       1970-01-01 01:00:00.000000000
+0100
+++ grub2-pci_etherboot/drivers/pci/pci_etherboot.c     2006-05-16
21:31:47.000000000 +0100
@@ -0,0 +1,296 @@
+/* pci_etherboot.c -  PCI implementation,  Adapted from Etherboot */
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+
+#include <grub/pci.h>
+#include <grub/misc.h>
+#include <grub/dl.h>
+#include <etherboot/pci_defs.h>
+#include <etherboot/cpu/limits.h>
+
+extern struct grub_pci_io_support grub_pci_io_support_etherboot;
+
+/*
+ *     Set device to be a busmaster in case BIOS neglected to do so.
+ *     Also adjust PCI latency timer to a reasonable value, 32.
+ */
+static void adjust_pci_device (grub_pci_device_t p)
+{
+       unsigned short  new_command, pci_command;
+       unsigned char   pci_latency;
+
+       grub_pci_io_support_etherboot.read_config_word (p,
+      PCI_COMMAND, &pci_command);
+       
+  new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
+       
+  if (pci_command != new_command)
+  {
+    /*  PCI BIOS has not enabled this device! */
+               grub_pci_io_support_etherboot.write_config_word (p,
+        PCI_COMMAND, new_command);
+       }
+       
+  grub_pci_io_support_etherboot.read_config_byte (p,
+      PCI_LATENCY_TIMER, &pci_latency);
+       
+  if (pci_latency < 32)
+  {
+               grub_pci_io_support_etherboot.write_config_byte (p,
+        PCI_LATENCY_TIMER, 32);
+       }
+}
+
+/*
+ * Find the start of a pci resource.
+ */
+static unsigned long pci_bar_start (grub_pci_device_t dev, unsigned int
index)
+{
+       grub_uint32_t lo, hi;
+       unsigned long bar;
+       grub_pci_io_support_etherboot.read_config_dword (dev, index, &lo);
+       if (lo & PCI_BASE_ADDRESS_SPACE_IO)
+  {
+               bar = lo & PCI_BASE_ADDRESS_IO_MASK;
+       } else
+  {
+               bar = 0;
+               if ((lo & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64)
+    {
+                       grub_pci_io_support_etherboot.read_config_dword (dev, 
index + 4, &hi);
+                       if (hi)
+      {
+#if ULONG_MAX > 0xffffffff
+                               bar = hi;
+                               bar <<=32;
+#else
+                               grub_printf ("Unhandled 64bit BAR %08x:%08x\n", 
hi, lo);
+                               return -1UL;
+#endif
+                       }
+               }
+               bar |= lo & PCI_BASE_ADDRESS_MEM_MASK;
+       }
+
+       return bar + grub_pci_io_support_etherboot.bus_base (dev->bus);
+
+}
+
+/*
+ * Find the size of a pci resource.
+ */
+static unsigned long pci_bar_size (grub_pci_device_t dev, unsigned int bar)
+{
+       grub_uint32_t start, size;
+       /* Save the original bar */
+       grub_pci_io_support_etherboot.read_config_dword(dev, bar, &start);
+       /* Compute which bits can be set */
+       grub_pci_io_support_etherboot.write_config_dword(dev, bar, ~0);
+       grub_pci_io_support_etherboot.read_config_dword(dev, bar, &size);
+       /* Restore the original size */
+       grub_pci_io_support_etherboot.write_config_dword(dev, bar, start);
+       /* Find the significant bits */
+       if (start & PCI_BASE_ADDRESS_SPACE_IO) {
+               size &= PCI_BASE_ADDRESS_IO_MASK;
+       } else {
+               size &= PCI_BASE_ADDRESS_MEM_MASK;
+       }
+       /* Find the lowest bit set */
+       size = size & ~(size - 1);
+       return size;
+}
+
+/*
+  pci_find_capability - query for devices' capabilities
+  @dev: PCI device to query
+  @cap: capability code
+
+  Tell if a device supports a given PCI capability.
+  Returns the address of the requested capability structure within the
+  device's PCI configuration space or 0 in case the device does not
+  support it.  Possible values for @cap:
+
+   %PCI_CAP_ID_PM           Power Management
+
+   %PCI_CAP_ID_AGP          Accelerated Graphics Port
+
+   %PCI_CAP_ID_VPD          Vital Product Data
+
+   %PCI_CAP_ID_SLOTID       Slot Identification
+
+   %PCI_CAP_ID_MSI          Message Signalled Interrupts
+
+   %PCI_CAP_ID_CHSWP        CompactPCI HotSwap
+ */
+static int pci_find_capability (grub_pci_device_t dev, int cap)
+{
+       grub_uint16_t status;
+       grub_uint8_t pos, id;
+       grub_uint8_t hdr_type;
+       int ttl = 48;
+
+       grub_pci_io_support_etherboot.read_config_word(dev, PCI_STATUS, 
&status);
+       if (!(status & PCI_STATUS_CAP_LIST))
+               return 0;
+       grub_pci_io_support_etherboot.read_config_byte(dev, PCI_HEADER_TYPE,
&hdr_type);
+       switch (hdr_type & 0x7F)
+  {
+    case PCI_HEADER_TYPE_NORMAL:
+    case PCI_HEADER_TYPE_BRIDGE:
+    default:
+      grub_pci_io_support_etherboot.read_config_byte(dev,
PCI_CAPABILITY_LIST, &pos);
+               break;
+    case PCI_HEADER_TYPE_CARDBUS:
+      grub_pci_io_support_etherboot.read_config_byte(dev,
PCI_CB_CAPABILITY_LIST, &pos);
+               break;
+       }
+
+       while (ttl-- && pos >= 0x40)
+  {
+               pos &= ~3;
+    /* Read cpability in ID */
+               grub_pci_io_support_etherboot.read_config_byte(dev, pos +
PCI_CAP_LIST_ID, &id);
+
+               if (id == 0xff)
+                       break;
+               if (id == cap)
+                       return pos;
+               grub_pci_io_support_etherboot.read_config_byte(dev, pos +
PCI_CAP_LIST_NEXT, &pos);
+       }
+       return 0;
+}
+
+/*
+ For each PCI device, HOOK will be called with the following
+ fields of the grub_pci_device structure set:
+    bus, devfn, vendor, dev_id, class
+
+ If you happen to be interested in a particular device,
+ malloc a new one, copy the fields above and initialise the
+ remaining fields with init_pdev (dev).
+*/
+static grub_err_t iterate (grub_err_t (*hook) (grub_pci_device_t))
+{
+  struct grub_pci_device pdev;
+  grub_uint32_t l;
+  unsigned int bus,devfn;
+  unsigned char hdr_type = 0;
+
+
+       /*
+   Scan all PCI buses, until we find our card.
+        We could be smart only scan the required buses but that
+        is error prone, and tricky.
+        By scanning all possible pci buses in order we should find
+        our card eventually.
+        */
+
+#define NBUSES 256
+#define NBFN   256
+
+  for (bus = 0; bus < NBUSES; bus++)
+  {
+    pdev.bus = bus;
+               for (devfn = 0; devfn < NBFN; devfn++)
+    {
+      pdev.devfn = devfn;
+                       if (PCI_FUNC (devfn) == 0)
+                               
grub_pci_io_support_etherboot.read_config_byte(&pdev,
+            PCI_HEADER_TYPE, &hdr_type);
+                       else if (!(hdr_type & 0x80))    /* not a multi-function 
device */
+                               continue;
+
+                       grub_pci_io_support_etherboot.read_config_dword(&pdev,
+          PCI_VENDOR_ID, &l);
+
+                       /* some broken boards return 0 if a slot is empty: */
+                       if (l == 0xffffffff || l == 0x00000000)
+                               continue;
+
+                       
+      pdev.vendor = l & 0xffff;
+      pdev.dev_id = (l >> 16) & 0xffff;
+
+      grub_pci_io_support_etherboot.read_config_dword(&pdev,
+          PCI_REVISION, &l);
+                       
+      pdev.class = (l >> 8) & 0xffffff;
+
+      hook (&pdev);
+    }
+  }
+  return GRUB_ERR_NONE;
+}
+
+static grub_err_t
+init_pdev (grub_pci_device_t dev)
+{
+  grub_uint32_t membase, ioaddr, romaddr;
+  grub_uint8_t irq;
+  int reg;
+
+                       
+       /* Get the ROM base address */
+       grub_pci_io_support_etherboot.read_config_dword(dev, PCI_ROM_ADDRESS,
&romaddr);
+       romaddr >>= 10;
+       dev->romaddr = romaddr;
+       
+       /* Get the ``membase'' */
+       grub_pci_io_support_etherboot.read_config_dword(dev,
PCI_BASE_ADDRESS_1, &membase);
+       dev->membase = membase;
+               
+       /* Get the ``ioaddr'' */
+       for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4)
+    {
+      grub_pci_io_support_etherboot.read_config_dword(dev, reg, &ioaddr);
+      if ((ioaddr & PCI_BASE_ADDRESS_IO_MASK) == 0 ||
+          (ioaddr & PCI_BASE_ADDRESS_SPACE_IO) == 0)
+        continue;
+               
+               
+      /* Strip the I/O address out of the returned value */
+      ioaddr &= PCI_BASE_ADDRESS_IO_MASK;
+               
+      /* Take the first one or the one that matches in boot ROM address */
+      dev->ioaddr = ioaddr;
+    }
+
+       /* Get the irq */
+       grub_pci_io_support_etherboot.read_config_byte(dev, PCI_INTERRUPT_PIN,
&irq);
+       if (irq)
+               grub_pci_io_support_etherboot.read_config_byte(dev,
PCI_INTERRUPT_LINE, &irq);
+       
+       dev->irq = irq;
+
+  return GRUB_ERR_NONE;
+}
+
+struct grub_pci_support grub_pci_support_etherboot =
+{
+.name = "Etherboot PCI support",
+.init = 0,
+.fini = 0,
+.adjust = adjust_pci_device,
+.bar_start = pci_bar_start,
+.bar_size = pci_bar_size,
+.find_capability = pci_find_capability,
+.iterate = iterate,
+.init_pdev = init_pdev,
+.io = &grub_pci_io_support_etherboot
+};
+
+GRUB_MOD_INIT(pci_etherboot)
+{
+  (void)mod;                   /* To stop warning. */
+  grub_set_pci_support(&grub_pci_support_etherboot);
+}
+
+GRUB_MOD_FINI(pci_etherboot)
+{
+  grub_unset_pci_support(&grub_pci_support_etherboot);
+}




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