confused by emacs verilog mode

[chenyong20000]

Hi,

I'm trying to use emacs verilog mode for vi. I have a piece of code like this:

    fifo_half_entry AUTO_TEMPLATE (
                         .shift_datain_r        (dataout0_r_entry_@"(+ 1 @)"),
                         .shift_datain_f        (dataout0_f_entry_@"(+ 1 @)"),
                         .dataout_r             (dataout0_r_entry_@),
                         .dataout_f             (dataout0_f_entry_@),
                         .datain_r              (rddata_in_r[3:0]),
                         .datain_f              (rddata_in_f[3:0]),
                         .fifo_write            (fifo_write0_@),
                         .fifo_shift            (gather_pop),
                         .rst_n                 (rst_n_propgt),
                         .clear_fifo            (clear_fifo_R),
     );
     */
    fifo_half_entry inst_gather_fifol_entry_0 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifol_entry_1 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifol_entry_2 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifol_entry_3 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifol_entry_4 (/*AUTOINST*/);  
    /* fifo_half_entry AUTO_TEMPLATE (
                         .shift_datain_r        (dataout1_r_entry_@"(+ 1 @)"),
                         .shift_datain_f        (dataout1_f_entry_@"(+ 1 @)"),
                         .dataout_r             (dataout1_r_entry_@),
                         .dataout_f             (dataout1_f_entry_@),
                         .datain_r              (rddata_in_r[7:4]),
                         .datain_f              (rddata_in_f[7:4]),
                         .fifo_write            (fifo_write1_@),
                         .fifo_shift            (gather_pop),
                         .rst_n                 (rst_n_propgt),
                         .clear_fifo            (clear_fifo_R),
     );
     */
    fifo_half_entry inst_gather_fifoh_entry_0 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifoh_entry_1 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifoh_entry_2 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifoh_entry_3 (/*AUTOINST*/);  
    fifo_half_entry inst_gather_fifoh_entry_4 (/*AUTOINST*/);

what confused me is that after generate code, it seems like this:

     fifo_half_entry AUTO_TEMPLATE (
                         .shift_datain_r        (dataout0_r_entry_@"(+ 1 @)"),
                         .shift_datain_f        (dataout0_f_entry_@"(+ 1 @)"),
                         .dataout_r             (dataout0_r_entry_@),
                         .dataout_f             (dataout0_f_entry_@),
                         .datain_r              (rddata_in_r[3:0]),
                         .datain_f              (rddata_in_f[3:0]),
                         .fifo_write            (fifo_write0_@),
                         .fifo_shift            (gather_pop),
                         .rst_n                 (rst_n_propgt),
                         .clear_fifo            (clear_fifo_R),
     );
     */
    fifo_half_entry inst_gather_fifol_entry_0 (/*AUTOINST*/
                                                                 // Outputs
        .dataout_r              (dataout1_r_entry_0), // Templated
        .dataout_f              (dataout1_f_entry_0), // Templated
                                                                 // Inputs
        .clk                    (clk),
        .rst_n                  (rst_n_propgt),  // Templated
        .datain_r               (rddata_in_r[7:4]), // Templated
        .datain_f               (rddata_in_f[7:4]), // Templated
        .shift_datain_r (dataout1_r_entry_1), // Templated
        .shift_datain_f (dataout1_f_entry_1), // Templated
        .fifo_write             (fifo_write1_0), // Templated
        .fifo_shift             (gather_pop),    // Templated
        .clear_fifo             (clear_fifo_R));         // Templated  
    fifo_half_entry inst_gather_fifol_entry_1 (/*AUTOINST*/
                                                                 // Outputs
        .dataout_r              (dataout1_r_entry_1), // Templated
        .dataout_f              (dataout1_f_entry_1), // Templated
                                                                 // Inputs
        .clk                    (clk),
         .rst_n                 (rst_n_propgt),  // Templated


you can find from these code that the dataout0_r_entry_xxx has been changed 
from dataout0 to dataout1. I don't know how this happens and how can i get 
right code. Can anybody help me? thanks.


regards