Re: Preprocessing files with make

[Michael Chastain]

>   mc> alpha.o: %.o
>   mc> cc -c $< -o $@ -DFOO
>
>   mc> I didn't write this.  Check my mail again.
>
> ???
>
> I quoted you exactly... I'm not in the habit of reworking peoples' email
> and then quoting it.

Ah, I see.  I wrote an actual Makefile and tested it, but then I
misquoted it myself in the fragement.  Here's another copy, just for
clarity.

===

C_FILES := $(wildcard *.c)
O_FILES := $(patsubst %.c,%.o,$(C_FILES))

dep_list_alpha  := alpha.h
dep_list_beta   := beta1.h beta2.h
dep_list_gamma  := gamma.h

a.out: $(O_FILES)
        cc $(O_FILES) -o $@

$(O_FILES): %.o: %.c $(wildcard %*.h) $(dep_list_%)
        cc -c $< -o $@

alpha.o:
        cc -c $< -o $@ -DFOO

===

> You can do this kind of thing in GNU make 3.80, with the $(eval ...)
> function.

That will be cool.

I haven't upgraded to 3.80 yet, because "build.sh" does not work.
I've been waiting for 3.80.1 or 3.81.

Michael