included makefiles

[Reynolds, John]

Hi,

I have an application development kit that provides me with a template make file named "makefile". Its contents are something like this:

APP_NAME        := myapp

APP_SRCS        := myAppMain.c \
                screen1.c \
                screen2.c

include ../appmake.make

If I do nothing more than type "make" at the command line, makefile is read, ../appmake.make is read and because no targets are specified, the default "help" target message is echoed:

Please specify a build configuration.

The following configurations are supported:

    prd-ddk-1-ptv
    prd-ddk-1-rom
    prd-ddk-1-ram
    prd-ddk-1-rel
    dev-ddk-1-ptv
    dev-ddk-1-rom
    dev-ddk-1-ram
    dev-ddk-1-rel
    dev-ddk-1-abs

I have complete control over makefile. In fact, I need to edit it so that my source files are included in the variable APP_SRCS. I should not change appmake.make because it can be overwritten during updates to the development kit.

I need to conditionally compile sections of my code depending on whether I am building a development version or a production version. I can do this by invoking make with a -Dproduction=1.

At a minimum, I'd like to echo a line like "add -Dproduction=1 after the target name to build a production version" as a reminder every time make is run.

Ideally, I'd like to add some logic to the template makefile that I have control over so that I can intercept the target name, set the variable and then include ../appmake.make.

Any ideas?

Sorry for the long post. Any help would be appreciated.

John

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