RE: Call with computed variable names

[David Kilroy]

Noel Yap wrote:
> Might I suggest another approach?  Rather than having the caller
> define such variables as FOO_TGT, FOO_OBJS, ..., why not just have
> the caller pass in these values directly into the function?  

I had been doing this to make things nice and clean, but..
 
> Also, IME, defining variables within functions leads to unscalable
> functions.  Eventually, the variables get redefined at the most
> inopportune moment.  If you really need to define variables, the
> suggested coding style for temporary variables is to use lower case
> letters.  Given these, your function becomes:   

I agree that this is sensible, so I'm no longer setting variables in the
function.

> Ken Smith wrote:
>> On Thu, Sep 16, 2004 at 05:00:32PM +0100, David Kilroy wrote:
>>> My new problem, still related to computed variables, eval, call and
>>> friends is shown below. In this case the dependencies of a target
>>> do not appear to be expanded correctly.
>> 
>> These things are tricky.  I have been recently wrestling with very
>> similar issues.  Here's the fix.
>> 
>> $$($(1)_TGT) : $$($(1)_OBJS)

Funnily enough, that was my first attempt. Now I try it with my minimal test
case, it does indeed work. However in my main tree:

dkilroy
$ make
make: *** virtual memory exhausted.  Stop.

Again I've come up with a test case. The tree I'm working with dumps the
objects into a different directory to the source, all in directories below
the makefile. Each module has it's own directory and both source and objects
for that module are contained somewhere there. That's why I'm using the
addprefix, though it may not be this that is causing the problem. Reducing
the number of source files makes the problem go away.

Anyway, here's the testcase:

dkilroy
$ cat makefile

OBJ_PATH:=bar
FOO_SRCS:=foo.c foo2.c foo3.c foo4.c foo5.c foo6.c foo7.c foo8.c foo9.c

define TEMPLATE
dir/$(2)/$(OBJ_PATH)/$(2).lno : $$(addprefix dir/$(2)/$(OBJ_PATH)/,
$$($(1)_SRCS:.c=.obj))
endef

all: dir/tmp/bar/tmp.lno
        @echo Sources are $(FOO_SRCS)

$(eval $(call TEMPLATE,FOO,tmp))

%.obj:
        @echo Making $@

%.lno:
        @echo Making $@

dkilroy
$ make -d
GNU Make 3.80
Copyright (C) 2002  Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
Reading makefiles...
Reading makefile `Makefile'...
make: *** virtual memory exhausted.  Stop.