RE: (no subject)

[Praveen SINGH]

Hi Greg,

Thanks.

I need to elobarate little more.
below is my chunk of code:

export BASE:=yyy_BASE

...
dirs: 
        mkdir -p $(OBJ)
        cd $(SUBDIR_1) && $(MAKE)
        cd $(SUBDIR_2) && $(MAKE) TARGET=$(BASE)


And I build like "make TARGET=xxx_BASE". Actually for second sub dir build I 
wan to redfine "TARGET". where TARGET is a command line argument.
But the above statement is not working. what can be missing?


Best Regards,
Praveen


-----Original Message-----
From: Greg Chicares [mailto:address@hidden 
Sent: Wednesday, September 07, 2005 12:53 AM
To: Praveen SINGH
Cc: address@hidden
Subject: Re: (no subject)


On 2005-9-5 5:36 UTC, Praveen SINGH wrote:
> There is a define (xxx_BASE) declared in (_mB). This xxx_BASE is used 
> in both the makefiles. I run my _mB to make which inturn internally 
> calls _mA. I get a sort of error "define xxx_BASE is not found" in 
> making _mA. To avoid this I declared the xxx_BASE in _mA also. But 
> that's code duplicay.

In the first makefile, pass the definition to the second makefile.

        $(MAKE) -f _mA xxx_BASE='$(xxx_BASE)' [target to make in _mA]