I've looked through the make docs, but haven't found an answer to
this: is there a way to tell make that "this rule works for these
kinds of targets, but the commands must be run separately for each"?
For instance, consider the last rule in the following Makefile:
---------
all: out-a out-b out-c out-d
SRC=$(wildcard src/*.c)
out-a: $(SRC:%.c=%.ao)
out-b: $(SRC:%.c=%.bo)
out-c: $(SRC:%.c=%.co)
out-d: $(SRC:%.c=%.do)
%.ao: TYPE=A
%.bo: TYPE=B
%.co: TYPE=C
%.do: TYPE=D
out-%:
gcc -o $@ $^
%.ao %.bo %.co %.do : %.c
gcc -DTYPE=${TYPE} -c -o $@ $<
---------
This works as long as I make each final target (out-%) separately, but
if I run "make all", it thinks that the last rule makes all four
target types simultaneously, which is not the case. So I have to run
"make" four times to make all four targets.
I understand that the "multiple targets in a rule" example in the docs
(bigoutput/littleoutput) only works for explicit rules and that I
should use static pattern rules otherwise, but I just can't see how I
would write such a rule in my case. I need to have four different
types of object files made using the same commands with slightly
different options.
While I could just copy the last rule for times for the four different
types, in my actual Makefile, the commands are much more complex and
the file would become unwieldy and harder to maintain if I had to make
sure to make all changes to all versions of the same commands.
So is there another way of doing this more efficiently that I just
can't see?