Re: looking for help with auto creating rules with eval hierarchically

[John Graham-Cumming]

PATTON, BILLY (SBCSI) wrote:
> As the best of my understanding of what you sent, ${BB_${proj}}, the
> following should work.
> PROJECTS := lde ldg ldm ldf ldw lbf ldb
> BB_lde := a
> BB_ldg := b c
> BB_ldm := d e f
> BB_ldf := g h i j
> BB_ldw := k l n m o
> BB_lbf := p q r s t u
> BB_ldb := v w x y z aa ab
>
> .PHONY : all $(addprefix BB_ , ${PROJECTS})

This line will expand to

    .PHONY: all BB_ lde BB_ ldg BB_ ldm BB_ ldf BB_ ldw BB_ lbf BB_ ldb

Firstly there's a space after BB_ which I don't think you want and 
secondly I'm not sure that you mean that BB_lde (for example) is a 
target; isn't it that the things in $(BB_lde) are you targets?


> define bb_template
>  $(1): ; echo $(1)
> endef
>
> all : $(addprefix BB_ , ${PROJECTS})

So this line is:

    all : BB_ lde BB_ ldg BB_ ldm BB_ ldf BB_ ldw BB_ lbf BB_ ldb

Even if you eliminate the space after the _ and get

    all : BB_lde BB_ldg BB_ldm BB_ldf BB_ldw BB_lbf BB_ldb

Is that really what you want?

> $(foreach proj,$(PROJECTS), $(eval $(call bb_template,$(BB_$(proj)))))

This ends up calling bb_template on each of $(BB_lde), $(BB_ldg), ... 
etc.  If you take, for example, $(BB_ldg) that's b c.  So it does

    $(call bb_template,b c)

which is

    b c: ; @echo b c

Which is then $(eval)ed which means that GNU Make ends up defining the 
following two rules:

    b: ; @echo b c
    c: ; @echo b c

Once again I don't think that's what you intended.  This came about 
because of the elimination of my second foreach loop.

> But it doesn't.  I get missing seperator pointing to the line after all:

Probably because you've got a blank link between the all: line and the 
$(foreach ...) line.

John.
--
John Graham-Cumming
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