Re: how to deal if source code and object file are in different directory?

[Philip Guenther]

On 8/31/06, Lin George <address@hidden> wrote:
> I have read related parts of GNU Make manual and it is
> very informative. I have also updated my Makefile
> according to your comments. Please help to check
> whether it is better now. :-)
>
> SRC_DIR=src
> OBJ_DIR=debug
> SRC=foo.c goo.c
> OBJ=goo.o goo.o
>
> I think in this way, it is more elegant according to
> your comments. Agree?

The names are clearer.  Whether it's useful to separate the directory
name from the file names depends on what you're trying to accomplish.
Generating OBJ from SRC via
   OBJ = $(SRC:.c=.o)
or vice-versa may eliminate a possible source of error.

Then again, what rules actually need the SRC variable at all?  In the
build system for the main project I work on we don't list .c files in
the Makefiles at all, while only generated .h files that need to be
created before normal compiles (e.g., y.tab.h) are listed.  The
primary list of files is the list of objects needed for each library
or program: pattern rules deduce the source automatically while
automatic dependency generation handles the dependencies on random .h
files.


> Then, I think I need a rule to compile foo.c and goo.c
> from src directory into foo.o and goo.c to debug
> directory. Do you know how to write such a rule?

If any .o file in $(OBJ_DIR) should be built from the matching .c file
in $(SRC_DIR), use this:

$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
       $(COMPILE.c) -o $@ $<


The static pattern rule version that would only do that for $(OBJ)
would look like:

$(OBJ:%=$(OBJ_DIR)/%): $(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
       $(COMPILE.c) -o $@ $<


Philip Guenther