help-make
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Expanding a variable in the dependencies


From: Or Goshen
Subject: Expanding a variable in the dependencies
Date: Wed, 18 Jul 2007 22:41:26 +0300

Hi

I have the following make file:
TEST_LO=test.lo
 
%.so: $($*_LO)
$(CC) $(LDFLAGS) -shared -Wl,-soname,$*.so.0 -o $*.so $($*_LO)
 
%.lo: %.c
$(CC) $(CFLAGS) -fPIC -o $*.lo -c $*.c

When I execute "make TEST.so" I get:
$ make TEST.so
gcc -shared -Wl,-soname,TEST.so.0 -o TEST.so test.lo
gcc: test.lo: No such file or directory
make: *** [TEST.so ] Error 1
My question is - why doesnt it expand "$($*_LO)" in the dependencies as well ?
(I got the file "test.c" in the directory)


reply via email to

[Prev in Thread] Current Thread [Next in Thread]