Re: using variables in makefile

[Paul Smith]

On Thu, 2010-03-04 at 23:11 -0800, mahmoodn wrote:
> In my makefile I have these lines:
> GPGPUSIM_ROOT := $(GPGPUSIM_ROOT)
> include $(NVIDIA_CUDA_SDK_LOCATION)/C/common/common.mk
> 
> I have set two variables in bash.rc file. The results for echo are:
> address@hidden:~$ echo $GPGPUSIM_ROOT
> /home/mahmood/gpgpusim/gpgpu-sim_v2.1.1b
> 
> address@hidden:~$ echo $NVIDIA_CUDA_SDK_LOCATION
> /home/mahmood/NVIDIA_GPU_Computing_SDK
> 
> Now when I run the makefile I get this error:
> Makefile:<line number>: /C/common/common.mk: No such file or directory
> make: *** No rule to make target `/C/common/common.mk'.  Stop.

Are you sure you exported those variables?  Just echo won't tell you
that.

Try this:

        env | grep NVIDIA_CUDA_SDK_LOCATION

This works because env is a separate program (like make is) so it can
only print the environment which is exported from your shell to its
children.

If the above command shows the value you want, then I'm stumped because
what you're doing should work.  If it doesn't, then you've forgotten to
export; in your ~/.bashrc use the "export" directive:

        export NVIDIA_CUDA_SDK_LOCATION=$HOME/NVIDIA_GPU_Computing_SDK

I recommend, to make your makefile more robust, you check to be sure the
variable is set and use $(error ...) to fail if not.

-- 
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 Paul D. Smith <address@hidden>          Find some GNU make tips at:
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