I was wondering if someone has solved the following recursive ascend problem.
Lets say, we have a list of environment variables to export.. Obviously we can put these in a file and either include them or source them. Obviously, if one begins from the top of a src tree, this operation (or inclusion) will be placed in the top level Makefile, aka $SRC_ROOT/Makefile
However, what if we are at some arbiterary place in the src tree, say $SRC_ROOT/a/b/c and we want to build. In this situation, most solutions I have seen consists of a hard coded (or static) solution where for example $SRC_ROOT/a/b/c/Makefile would say something like
Note how the path is static. This is not a clean design, as if you change the shape of the source tree, then all these static references need to be updated. A cleaner design is a recursive ascend, just like OO languages and how then find appropriate implementations of a code. More specifically, each Makefile at a given node (or level) only knows about its parent, something like. For example, lets say the top level Makefile has a target call "init", then each non top level Makefile can say
$(MAKE) -C ../ init
I hope this has provided a sufficient background....now my attempt to solve this...which is not working
first I'll set up a test environment consisting of a few dirs and sub-dirs
this: @echo "in address@hidden" -----------------------------------------
cat a/Makefile
default: test
.PHONY: init init: $(MAKE) -C ../ init
test: @pwd @echo "value of X=[$X]"
------------------------------
So the idea I was trying is to have a target called "init" in every makefile. I want to this target to be executed every time. In top level makefile, this target will include or source some env vars. In non top level makefiles, it calls the parent. Hence a recursive ascend.