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RE: intentional missing prerequisites?


From: Canham, Timothy K (316C)
Subject: RE: intentional missing prerequisites?
Date: Tue, 31 Aug 2010 10:00:40 -0700

Thanks for your suggestions. I actually sort of figured out a way to do it.

In the general rule area of the master makefile, just define an empty target:

big_target:

In the users local make file that gets included:

big_target: target_1

target_1:
        do something

...

big_target: target_2

target_2:
        do something else


This actually works pretty well because the master make file doesn't need to be 
modified when there is a new sub-target because make merges the prerequisites. 
It is only a local change for the user.




Timothy K. Canham
Jet Propulsion Laboratory
Pasadena, CA
address@hidden


> -----Original Message-----
> From: Mike Shal [mailto:address@hidden
> Sent: Tuesday, August 31, 2010 9:25 AM
> To: Canham, Timothy K (316C)
> Cc: address@hidden
> Subject: Re: intentional missing prerequisites?
> 
> On Tue, Aug 31, 2010 at 11:46 AM, Canham, Timothy K (316C)
> <address@hidden> wrote:
> > We have a modular make system where we would like to be allow users
> to add and remove build targets.
> >
> > What I would like to be able to do is something like this:
> >
> > big_target: target_1 target_2 target3
> >
> >
> > target_1:
> >        do something
> >
> > target_2:
> >        do something else
> >
> > and target_3 is not defined anywhere.
> >
> > I would like to know if there is a way to make the definition of the
> prerequisite target optional, and not break the rule. I know I could
> do:
> >
> > target_3:
> >
> > and it would work, but that would require adding hundreds of them, so
> I'd like to avoid it.
> >
> > Any ideas?
> 
> I used to use a rule like this to ignore missing header files:
> 
> %.h:
>         @echo "  ??      $@"
> 
> The echo is just to let the user know that make couldn't find the
> header, but if that header is no longer actually required then the
> build will succeed. If the header is required, make should still try
> to build the dependent objects, and then the compile will fail for
> those.
> 
> I suppose you could try to generalize it like this:
> 
> %:
>         @echo "  ??      $@"
> 
> But that might have some serious unintended side-effects. If you can
> make all of these targets follow a pattern that you can wildcard it
> would probably be safer (like %.target or something, and use 1.target,
> 2.target, etc).
> 
> -Mike



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