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Having <<one>> makefile compiling code in sevreal subdirs

From: zainka
Subject: Having <<one>> makefile compiling code in sevreal subdirs
Date: Mon, 31 Jan 2011 03:56:25 -0800 (PST)


I have tried to understand how to create a makefile in my project root
folder which compiles source found in its subdirectories. I want to do this
with only one main makefile where all rules and such are contained not
having a lot of sub makefiles that is recursively called. 

That is, I DO have files in the subdirectories which i includes from the
root makefile, but I only allow this to add source paths to my SRC variable
and to include other sub-subdirectories and include dirs. This is done in
makefiles i name and which I includes from within the root

Since I get the No rule to make target error, the error is most certainly
that makefile do not find a rules dependency. Here I am certain that the
problem is that the source files are not found.

In the makefile. The first rule that is invoked by "make all" is the elf
rule where elf: is depending on @(TARGET).elf 

elf: $(TARGET).elf

This is in turn invoking the rule

%.elf:  $(OBJ)
   @echo $(MSG_LINKING) $@
   $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS)

As in turn will invoke the rules given by variable OBJ...
OBJ is a variable that represents three dependencies for rule %.elf: as seen

OBJ = $(SRC:./%.c=$(OBJDIR)/%.o) $(CPPSRC:./%.cpp=$(OBJDIR)/%.o)

Where SRC is a concatenated list from the earlier mentioned included files. The list is accurate seen from project root folder and
partly listed here:

SRC= ./apps/display-demo/main.c ./apps/display-demo/app_desktop.c
./apps/display-demo/app_calibrate.c ./apps/display-demo/app_calc.c
./apps/display-demo/app_clock.c ./apps/display-demo/app_fonts.c

This gives a list of objs that is to long to insert here, but here is a

OBJ=.obj/apps/display-demo/main.o .obj/apps/display-demo/app_desktop.o
.obj/apps/display-demo/app_calibrate.o .obj/apps/display-demo/app_calc.o
.obj/apps/display-demo/app_clock.o .obj/apps/display-demo/app_fonts.o
.obj/apps/display-demo/app_files.o  ..... 

Now, Look at how OBJ are defined --> $(SRC:./%.c=$(OBJDIR)/%.o) represents
the first rule dependencie, or rather $(OBJDIR)/%.o as seen in rule

$(OBJDIR)/%.o : %.c
   @echo $(MSG_COMPILING) $<
   $(CC) -c $(ALL_CFLAGS) $< -o $@

Well, that’s at-least the way I have understand it make will interpret it.
Now, This should give that the %, or stem if you prefers, should for first
source element in SRC (see SRC expanded above) be apps/display-demo/main and
therefore the rule should become for first element (where OBJDIR=.obj)

.obj/apps/display-demo/main.o : apps/display-demo/main.c
   @echo $(MSG_COMPILING) $<
   $(CC) -c $(ALL_CFLAGS) $< -o $@

This then fails to compil. I have used the $(warning ...) directive to find
where things hangs. I tried to change %.c to ./%.c to ensure that it is
referred with relative path from where make is issued.

Running commandline works
avr-gcc -c apps/display-demo/main.c -o .obj/apps/display-demo/main.o

This directly will start compilation of main. It seems to me that the value
of % is not passed??!!??

As mentioned. I have a structure where a makefile is stored in a project
folder, and in subdirectories of this projectfolder you find the source and
include files. Each subfolder contains a file which is adding
sourcefiles to the SRC variable etc. and including other subdirs if present.
The .obj and .dep is wanted to be generated as subdirs directly inside the
project root folder having all deps and objs stored. There are no source
files in the project root folder.

Reason for doing this is that I want to structure my project differently
from earlier where i back then had the makefile and all sources stored in
same folder messing things up when projects grows.

Any help will do. I attach the makefile . Hope I do not scare you with my
rather loooong posts. I just try to describe the problem accurately. makefile 
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