Question about override directive

[José Luis García Pallero]

Hello,
I have a problem with override directive. I don't understand its
behavior in this case:

Suppose I have three makefiles in a project: a compiler selector
makefile, a general driver makefile and a makefile that actually makes
the program.

1. The compiler selector makefile (Makefile.cmp) as it name says
selects the compiler. By default is gcc but if you pass the variable
TARGET with the value 'windows' selects the i586-mingw32msvc-gcc
compiler. This selection overrides the CC variable in order to force
the i586-mingw32msvc-gcc if you pass explicitly the CC variable at the
same time that TARGET=windows. At the end, the CC variable is
exported. The Makefile.cmp looks like:

CC=gcc
ifeq ($(TARGET),windows)
        override CC=i586-mingw32msvc-gcc
endif
export CC

2. The general driver makefile (Makefile) includes at start the
Makefile.cmp file and calls the real makefile in order to build the
program. It looks like:

include Makefile.cmp
hello:
        $(MAKE) -f Makefile.hello hello1

3. And the makefile for building the code (Makefile.hello in our
example) looks like (in our example only prints the name of the
selected compiler):

hello1:
        @echo "***********************************************************"
        @echo "************Hello, compiler is $(CC)***********************"
        @echo "***********************************************************"

My problem is that if I call make with the arguments make hello CC=gcc
TARGET=windows the selected compiler is 'gcc' instead of
'i586-mingw32msvc-gcc' (if I call only with make hello TARGET=windows
all runs OK). The result is correct only if I put explicitly the
variable CC inside the Makefile file:

include Makefile.cmp
hello:
        $(MAKE) -f Makefile.hello hello1 CC=$(CC)

But I think that this is an ugly way

I suppose that I'm using override or export directives in the wrong
way, but I don't know the reason. Any ideas?

Thanks

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José Luis García Pallero
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