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Re: Clarification Needed on -C option


From: Paul Smith
Subject: Re: Clarification Needed on -C option
Date: Fri, 02 Sep 2011 02:57:58 -0400

On Fri, 2011-09-02 at 10:37 +0530, Ajay Jain wrote:
> Hi Experts,
> 
> I use a make -C option in my top-level Makefile. This calls a leaf
> Makefile to build, and checks CONFIG variable. If it not specified, it
> assigns a default configuration to the same variable. The snippet is
> as follows.
> 
> ifeq ("$(CONFIG)","")
>  $(info CONFIG Not Specified)
>  CONFIG = $(DEFAULT_CONFIG)
>  $(info Setting CONFIG to Default : $(CONFIG))
> endif
> 
> I see that this snipped executes twice in every invocation of Make.

I don't see how that's possible (given the situation as you've described
it).  Instead I think that the make is being invoked twice and that's
why you see the variable being set twice.

This could happen for at least two reasons: first, your parent makefile
could be running the sub-make twice for some reason.  If you enable
debug (or at least ensure that you're printing directory changes and
don't have --no-print-directory set) you can see that.

Second, you could be "include"ing another makefile which is also a
target, and it's getting rebuilt then make is re-exec'ing itself.  Again
the debug output should help determine if that's the case.  Look up
"Remaking Makefiles" section in the manual for more info here.


If you don't think either of those is true then please provide a
_minimal_ test case that reproduces the issue so we can see what's going
on.

-- 
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 Paul D. Smith <address@hidden>          Find some GNU make tips at:
 http://www.gnu.org                      http://make.mad-scientist.net
 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist




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