Re: Re: Suffix Wildcard?

[Drew Hubl]

On 2012-10-30, Oleksandr Gavenko wrote:

>On 2012-10-30, Drew Hubl wrote:
>
>> I've read up on the wildcard '%' character, and it seems as though it
only
>> matches non-empty strings, which works great for rules like:
>>
>> %.o:%.c
>>     $(CC) $* -o $@
>>
>> but what I would like to do is match suffixes for targets, like:
>>
>> tb%:
>>     vlog -nologo -work work tb$*.v
>> [SKIP]
>> Whenever I try to make the plain "tb" target, the command that gets run
is
>> a bit unexpected:
>> vlog -nologo -work work tb.o.v
>>
>> When what I expected was:
>> vlog -nologo -work work tb.v
>>
>> Is there a similar wildcard character that also matches empty strings, or
>> can I turn off automatically inserting ".o" in place of the '%'?
>>
>Do you have tb.o or rules that make tb.o (for example from tb.c)??
>
>May be Implicit Rules in effect. Try disable it if you do not replay on it
(I
>put this in all of my Makefiles in order to explicitly define all rules):
>
>  SHELL = /bin/sh
>
>  # Disable built in pattern rules.  <=======
>  MAKEFLAGS += -r
>  # Disable built in variables.
>  MAKEFLAGS += -R
>  # Disable built in suffix rules.
>  .SUFFIXES:
>  # Default target.
>  .DEFAULT_GOAL = help
>
>But seems you have bad naming schema for files (Makefile best work with
unique
>prefixes and suffixes, in case of %.o and prefix% you have both match of
>prefix.o; rename files to %<prefix> or put them to separate directory to
make
>naming schema consistent).
>
>Hope this help.
>
>--
>Best regards!
>

Thanks for the help, Oleksandr, I appreciate it.

I am trying to compile Verilog code, not C/C++, so there are no
intermediate .o files, and no targets to make them.

I tried those options you gave, but none of them fixed the issue. It did
get me thinking though.

I don't know if the observed behavior is the intended behavior of make or
not, but I managed to work around it by adding an explicit rule for the tb
target like so:

tb:
     vlog -nologo -work work tb.v

Thanks again.