Re: Silently ignored command line options when assigned (not overrided) in makefile

[Dawid Gosławski]

Hi Paul,

I have some variables inside makefile without override directive. When
someone assigns it via command line (or in recursive make rule) rule set by
user is ignored. I want to detect if someone uses cmd line assignments and
warns about that this is forbidden.

Example:

Makefile:

test: A=1
test:
      @echo "A="$(A)

cmd line:
make -f Makefile test (no warning)
make -f Makefile test A=2 (warning)

One of method is to use "ifdef" test to check before assignment in makefile
if variable was already set and print warning about that. But I am curious
if there is any other method, some makefile flag or something ?

Br
Dawid


2014-06-24 18:53 GMT+02:00 Paul Smith <address@hidden>:

> On Tue, 2014-06-24 at 12:14 +0200, Dawid Gosławski wrote:
> > It's not a bug, it's planned and documented. However I want to know how
> to
> > give users some warning about that assignment ? Of course we can declare
> > something like that:
> >
> > ifdef CFLAGS
> > $(warning "CAN NOT OVERRIDE CFLAGS BY COMMAND LINE")
> > endif
> >
> > on the beginning of the makefile but is there any better option for that
> ?
> > With multilevel structure and a lot of variables that potentially coult
> be
> > overrided make should give any warning when not assigning values as uses
> > assumes.
>
> Hi Dawid.  I'm afraid I'm not quite able to follow the situation.
>
> A command-line setting of a variable will always take precedence over an
> assignment of that variable in the makefile, unless the makefile
> assignment uses the "override" directive.
>
> Are you saying that this is not working for you?
>
> Or are you saying you do not want to allow variables to be overridden in
> your environment?
>
> Or do you want to warn users if they do override these variables when
> they shouldn't?
>
> Or warn them if they do not override them when they should?
>
>


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