Avoid to recompile the target

[FanKe Meng]

Hi,


I'm writing a simple project now with the main Makefile and definitions in a 
directory and submakes in its sub-directories.


I write explicit rules to compile the source files into object files and the 
link all the object files into an executable file.


However, while there is no source file changed and make is triggered on the 
command line,the executable file will be updated each time


though the object files aren't compiled again. Is there a way to avoid it?


Any help are appreciated.


The Makefile and Makefile.def are here:


Makefile


all:


export all_apps :=


include Makefile.def
include sub1/Makefile
include sub2/Makefile


all : $(all_apps)




Makefile.def


def src_to_obj
$1 : $2
$(CC) -o $1 -c $2
endef


def make_app
$(eval objs := $(patsubst %.c, %.o, $1))
all_apps += $1
$1 : $(objs)
$(CC) -o $1 $(objs)       #### it will be run every time make is triggered on 
the command line. Any way to avoid it?
endef


Best regars
Richy Mong