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Automatic variable $< not working the way I think it should


From: David Barrass
Subject: Automatic variable $< not working the way I think it should
Date: Tue, 14 Jul 2015 09:20:43 +0100
User-agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20131104 Icedove/17.0.10

Hi,

I am looking for an answer to what I think is a simple question but have
not been able to find it in the official GNU make book (online or in the
FSF hardcopy for 3.79), the O'Reilly "Managing Projects with Make" book
or in John Graham-Cumming's book. I have also entered my query into the
GNU Make mailing list archive but nothing relevant has turned up there
either.

What I want to achieve is build a series of object files from a set of
.S,.s and .c source files. I have the source files spread across
different subdirectories but for simplicity of linking, want then to end
up in the same obj directory.

My Makefile successfully generates the list of source and object files,
all with the correct directory path prepended. I then ask Make to build
the object files using gcc (ARM cross-compiler as it happens) using a
simple pattern rule which looks like this:-

$(LIBOBJS) : $(LIBSRCLIST)
--->    $(TOOLPATH)/$(CC) -c -o $@ -I$(INCDIR) $<

This appears to work and the target obj directory gets filled with the
correctly-named module name and so the automatic variable $@ seems to be
working as I expect but the object files are all the same size and in
fact have all been created by compiling the first (and only first)
prerequisite in the list. My understanding is that $< gets the first
prerequsite from $(LIBSRCLIST), executes the rule and then moves no to
the next source file in the list.

Putting in some debug confirms that gcc always gets the name of the
first source file in LIBSRCLIST.

I also tried running make -d and redirecting the output into a text file
but looking through this, I confess that I don't actually understand
what the Make debug is trying to tell me. I am running GNU Make 3.81 on
a Debian GNU/Linux machine.

What have I missed? Can I actually achieve what I want and have Make
traverse the LIBSRCLIST, running GCC on each member in turn, building
the object file for each source?

LIBSRCLIST looks like this (truncated):-

../libsrc/standalone/asm_vectors.S ../libsrc/standalone/boot.S
../libsrc/devcfg/xdevcfg.c ...

Many thanks in anticipation of a reply. If the answer is not immediately
obvious and someone is willing to take a closer look, I can supply a
simplified Makefile.

What I want to achieve is a make system in a less complex form of JG-C's
"Recursive Make Reloaded" or non-recursive make template as described in
his book "The GNU Make book". I really don't want to write a recursive
Makefile but I want to be able to compile sources from various
subdirectories but have all the output end up in its own top-level
directory.

Best regards,

David Barrass




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