Re: Looking for nastiest makefile that uses function calls to make the makefile in memory...

[Dagobert Michelsen]

Hi Brian,

Am 17.03.2017 um 17:45 schrieb Brian Cowan <address@hidden>:
> I'm chasing down use cases for the $(call and $(eval functions to
> effectively build the makefile from macros in the makefile (or included
> files). I'm looking to stress-test the make tool I support, which supports
> GNU make syntax, but I'm finding that elementary usecases don't always
> suffice. So, if someone knows of a makefile-from-h**l they have fought
> with, I'd love to hear about it... If its in an open-source project, that
> would be even better…

We use some dynamic make rule generation where you have a couple of
definitions of the form
  VAR1 = val1 val2
  VAR2 = more stuff
which then generates an individual rule for each combination
  rule-var1-val1-var2-more
  rule-var1-val1-var2-stuff
  rule-var1-val2-var2-more
  rule-var1-val2-var2-stuff
with an arbitrary number of different variables and values. In each
subinvocation all variables are set to their respective values in
the invocation. The code uses a lot of define together with
$(eval $(call …)))

You can see it at
  https://buildfarm.opencsw.org/source/xref/opencsw/csw/mgar/gar/v2/gar.mk#104


Best regards

  — Dago


--
"You don't become great by trying to be great, you become great by wanting to 
do something,
and then doing it so hard that you become great in the process." - xkcd #896

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