Re: Bochs 2.0.2 and L4ka

[Farid Hajji]

Hi Laurent,

> > "The DE bit allows the Pentium+ to set breakpoints in I/O space using
> > the breakpoint registers. The R/W coding 10b is used to indicate that
> > the breakpoint is in I/O space on the Pentium+.  The 10b encoding was
> > marked as 'invalid' for pre-Pentium CPUs."
> 
> I've also checked in the intel doc. 
> If you set DE bit in CR4 to 1, access to DR4 and DR5 ( reserved debug 
> register ) cause an invalid opcode exception (#UD).
> if DE bit is set to 0, DR4 and DR5 are aliased to debug register DR6 and DR7.
> 
> I've checked bochs sources and it work like that.
> It is done by the function "void BX_CPU_C::MOV_DdRd(bxInstruction_c *i)" in 
> proc_ctrl.cc. 

yes, that's true. I'm not sure about the ramifications of all
of this though...

> > hmmm, breakpoints handling may be somewhat hairy to handle.
> > I withdraw my previous statement about implementing DE-bit fully.
> > Perhaps forcing DE bit to 1 would be okay, as long as
> > no kernel debugger in Hazelnut (or pistachio) needs it.
> 
> Do you know if bochs handle correctly breakpoints ?
> If so, i don't think there is more stuff to do with this DE bit.

No idea concerning bochs' breakpoint handling. I didn't touch
that at all ;).

Okay, so let's force DE bit and hope for the best.

Thank you again for the patch!

> Regards,
> 
> Laurent

-Farid.

-- 
Farid Hajji -- Unix Systems and Network Management.
http://www.farid-hajji.net/address.html
Quoth the Raven, "Nevermore." --Edgar Allan Poe.