Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[Simon Goldschmidt]

Jochen Strohbeck wrote:
> - RX/TX descriptors must be in non-cacheable memory to avoid race
> conditions. Alignment and padding is not necessary (?)

You can do with cached memory + flushing if you obey alignment, but it's 
probably not worth the work: if the driver is programmed well, you'll access 
every word only once.

> - RX/TX buffers must be in non-cacheable memory or can be in cacheable
> memory but require explicit cache clean/invalidate before/after GMAC
> DMAs and buffers must be aligned and padded to multiple of cache line size.

Right.

> [..]
> This sounds complicated to me.

It is. That's why ST supplied drivers do memcpy for TX and RX instead of 
zero-copy.

> Therefore my first and probably stupid
> idea was to use explicit RX buffers, place them in non-cacheable memory
> and use them for RX payload instead of an allocated buffer. Does this
> probably work ?

Yes. That's the ST way. And unless you know you need more performance, this 
will probably work well for production code.
You basically allocate enough TX and RX buffers so that your driver never runs 
out of such buffers and memcpy between these buffers and the pbufs.
Make sure you keep error statistics to know you don't run out of buffers, which 
would decrease transmission speed.

This should be fixed in one of the next versions, however.

It's still a good idea to update to the newest version of lwIP as soon as you 
can. Doing it later in development cycle is never a good idea ;-)

Simon